Digital data storage tape formatter

Claim 2

A formatter write device for a digital data storage system, said digital data storage system having a data bus, a main buffer, a frame buffer, a frame buffer bus, a microcontroller, and a head drum in communication with magnetic tape comprising: randomizer means for randomizing data, said randomizer means coupled to the data bus; track checksum means for computing a running track checksum, said track checksum means coupled to said randomizer means; data interleaving means for interleaving data, said data interleaving means coupled to said track checksum means; arbiter means for arbiting access to the frame buffer, said arbiter means coupled to frame buffer; C2 parity byte computing means for generating C2 parity bytes, said C2 parity byte computing means coupled to said interleaving means and said arbiter means; C1 parity byte computing means for generating C1 parity bytes, said C1 parity byte computing means coupled to the frame buffer bus; - 10conversion means for performing 8-10 coding conversion of data, said 8-10 conversion means coupled to the frame buffer bus; track format data generating means for generating track format data and for synchronizing data writing with the head drum means, said track format data generating means coupled to the frame buffer bus and to the head drum; and status register means for registering the status of a write operation, said status register means coupled to the microcontroller and to the frame buffer bus.

Claim 3

The formatter write device of claim 1 wherein said randomizer means is parallel-functional.

Claim 4

The formatter write device of claim 1 wherein said randomizer means performs randomization on the fly during data transfers from the main buffer to the frame buffer.

Claim 5

The formatter write device of claim 1 wherein said interleaving means performs interleaving on the fly during data transfers from the main buffer to the frame buffer.

Claim 6

The formatter write devices of claim 1 wherein said C1 parity byte computing means computers C1 parity bytes on the fly during data transfers from the frame buffer to the tape.

Claim 7

The formatter write device of claim 1 wherein said data is in DDS standard format.

Claim 8

A formatter read device for a digital data storage system (DDS), said DDS system having a frame buffer, a microcontroller, and read/write channel coupled to a data separator comprising: deserializer means for converting serial data from magnetic tape to parallel, said deserializer means coupled to the data separator; 8-10 decoder means for decoding said data, said 8-10 decoder means coupled to said deserializer means; track checksum means for performing track checksum on said data, said track checksum means coupled to said decoder 8-10 means; C1 syndrome generator means for computing C1 syndromes on the fly and for writing both data and syndromes into the frame buffer, said C1 syndrome generator means coupled to said track checksum means; frame buffer manager means for managing data transmitted to the frame buffer, said frame buffer manager means coupled to said C1 syndrome generator means; arbiter means for arbiting access to the frame buffer, said arbiter means coupled to said frame buffer manager means; and C2 error correction coding means for generating C2 error correction code, said C2 error correction coding means coupled to said frame buffer manager means and to said arbiter means.

Claim 9

A formatter read device for a digital data storage system (DDS), said DDS system having a frame buffer, a microcontroller, and read/write channel coupled to a data separator comprising: deserializer means for converting serial data from magnetic tape to parallel, said deserializer means coupled to the data separator; 8-10 decoder means for decoding said data, said 8-10 decoder means coupled to said deserializer means; track checksum means for performing track checksum on said data, said track checksum means coupled to said decoder 8-10 means; C1 syndrome generator means for computing C1 syndromes on the fly and for writing both data and syndromes into the frame buffer, said C1 syndrome generator means coupled to said track checksum means; frame buffer manager means for managing data transmitted to the frame buffer, said frame buffer manager means coupled to said C1 syndrome generator means; arbiter means for arbiting access to the frame buffer, said arbiter means coupled to said frame buffer manager means; and C2 error correction coding means for generating C2 error correction code, said C2 error correction coding means coupled to said frame buffer manager means and to said arbiter means.

Claim 10

The formatter read device of claim 7 wherein said track checksum means is independent from amy write operation track checksum.

Claim 11

In a digital data storage audio tape system having a host device interface unit that is coupled to a main data buffer manager, the main data buffer manager coupled to a main data buffer means, the digital data storage audio tape system further including a processor means, a tape drive unit, a read/ write channel, and a DMA channel bus, a formatter comprising: formatter interface means for interfacing the processor means, said formatter interface means coupled between said processor means and an internal processor bus; formatter sequencer means for sequencing data and data operations, said formatter sequencer means coupled to said internal processor bus and to the read/write channel; formatter buffer manager means for buffering data between said formatter interface means and said formatter sequencer means, said formatter buffer manager means coupled to said formatter sequencer means by an internal read/write bus and to said internal processor bus, and further coupled to the DMA channel bus; said formatter interface means including an address map decoder, ready logic, interrupt control, serial port handshake logic, and a plurality of registers including an interrupt, a serial port address/status, a serial port data, a Galois field value 1, a Galois field value 2, a Galois field result, a Galois square root, and a jumper input; said formatter sequencer means including a C1 parity generator, a C1 syndrome generator, a read/write sequencer, an encoder/decoder, an automatic track finding (ATF) pattern generator, and an ID parity, and a plurality of registers including a serial/deserializer (serdes) control 0, a serdes control 1, a status, two read track checksum, and a bit pointer, a state counter, a block counter, and a byte counter; and said formatter buffer manager means including a C2 parity generator, a C2 syndrome generator, a data path control, a buffer address generator, a direct memory access (DMA) arbitrator, a DMA handshake, and a randomizer, and a plurality of registers including a DMA controller control, SRAM access latch, two track 1 checksum, two track 2 checksum, an ECC control, a control pulse, a C2 block address, and a bad C1 block count.

Claim 12

In a digital data storage audio tape system having a host device interface unit that is coupled to a main data buffer manager, the main data buffer manager coupled to a main data buffer means, the digital data storage audio tape system further including a processor means, a tape drive unit, a read/ write channel, and a DMA channel bus, a formatter comprising: formatter interface means for interfacing the processor means, said formatter interface means coupled between said processor means and an internal processor bus; formatter sequencer means for sequencing data and data operations, said formatter sequencer means coupled to said internal processor bus and to the read/write channel; formatter buffer manager means for buffering data between said formatter interface means and said formatter sequencer means, said formatter buffer manager means coupled to said formatter sequencer means by an internal read/write bus and to said internal processor bus, and further coupled to the DMA channel bus; said formatter interface means including an address map decoder, ready logic, interrupt control, serial port handshake logic, and a plurality of registers including an interrupt, a serial port address/status, a serial port data, a Galois field value 1, a Galois field value 2, a Galois field result, a Galois square root, and a jumper input; said formatter sequencer means including a C1 parity generator, a C1 syndrome generator, a read/write sequencer, an encoder/decoder, an automatic track finding (ATF) pattern generator, and an ID parity, and a plurality of registers including a serial/deserializer (serdes) control 0, a serdes control 1, a status, two read track checksum, and a bit pointer, a state counter, a block counter, and a byte counter; and said formatter buffer manager means including a C2 parity generator, a C2 syndrome generator, a data path control, a buffer address generator, a direct memory access (DMA) arbitrator, a DMA handshake, and a randomizer, and a plurality of registers including a DMA controller control, SRAM access latch, two track 1 checksum, two track 2 checksum, an ECC control, a control pulse, a C2 block address, and a bad C1 block count.

Claim 13

The formatter of claim 9 further comprising tri-state and activity modes means for automatic test equipment testing.

Claim 14

In a digital data storage magnetic tape system for transmitting data between a host device and a tape drive unit, the system including a formatter coupled to a frame buffer having at least one buffer pointer, and a processor, a method for read-after-write checking to determine whether a track was successful written, comprising the steps of: (a) multiple buffering the frame buffer wherein the processor stores a copy of the frame which is being read-after-write checked while simultaneously processing new frames for writing; and (b) immediately rewriting an improperly written frame by changing the buffer pointer in the frame buffer and updating relevant sub data areas under instruction control of said processor.

Claim 15

In a digital data storage magnetic tape system for transmitting data between a host device and a tape drive unit, the system including a formatter coupled to a frame buffer having at least one buffer pointer, and a processor, a method for read-after-write checking to determine whether a track was successful written, comprising the steps of: (a) multiple buffering the frame buffer wherein the processor stores a copy of the frame which is being read-after-write checked while simultaneously processing new frames for writing; and (b) immediately rewriting an improperly written frame by changing the buffer pointer in the frame buffer and updating relevant sub data areas under instruction control of said processor.

Claim 16

In a digital data storage magnetic tape system for transmitting data between a host device and a tape drive unit having a read channel and a frame buffer, the data being accessed and encoded and decoded on a per frame and per track basis, and the data being in a main data area and subject to C1 error correction code, read track checksum, a method for read-after-write (RAW) checking comprising the steps of: re-writing a frame when more than a predetermined number of blocks in any area of either track of the frame have C1 syndromes indicating an error; calculating read track checksums as the data is transferred from the read channel to the frame buffer; and re-writing the frame when a track checksum discrepancy is found, thereby achieving re-writing of a bad frame after only one intervening frame.

Claim 17

In a digital data storage magnetic tape system for transmitting data between a host device and a tape drive unit having a read channel and a frame buffer, the data being accessed and encoded and decoded on a per frame and per track basis, and the data being in a main data area and subject to C1 error correction code, read track checksum, a method for read-after-write (RAW) checking comprising the steps of: re-writing a frame when more than a predetermined number of blocks in any area of either track of the frame have C1 syndromes indicating an error; calculating read track checksums as the data is transferred from the read channel to the frame buffer; and re-writing the frame when a track checksum discrepancy is found, thereby achieving re-writing of a bad frame after only one intervening frame.

Claim 18

The RAW checking method of claim 12 further comprising the steps of: re-computing the track checksums during the main data area read; comparing the track checksums with a stored value having been written for that track; and comparing the track checksum to the value read back from one good subdata block pair, thereby avoiding drop-ins in the main data area of the frame.

Claim 19

The RAW checking method of claim 13 wherein said track checksum checking acts on RAW data, thereby allowing more stringent RAW criteria resulting in higher data integrity.

Claim 24

The method of claim 16 wherein the transferring of the data group responsive to instruction control step comprises the steps of: initializing a DMA controller and a main data buffer manager and moving one frame of data from the main data buffer to the formatter through the main data buffer manager; randomizing each byte of the data; computing a running track checksum of transferred bytes of the data; interleaving each bytes of the data; and storing each byte of the data in the frame buffer.

Claim 25

The method of claim 17 wherein said randomizing step is performed in parallel.

Claim 26

The method of claim 17 wherein said randomizing step is performed on the fly before that data is written to frame buffer.

Claim 27

The method of claim 17 wherein said running track checksum step is computed on the fly before that data is written to said frame buffer.

Claim 28

The method of claim 17 wherein said interleaving step is performed on the fly before that data is written to the frame buffer.

Claim 29

The method of claim 17 wherein said C1 parity byte computation step is performed on the fly before that data is written to magnetic tape.

Claim 30

The method of claim 17 wherein said data code conversion step is performed on the fly as frames are transferred between said frame buffer and magnetic tape.

Claim 31

The method of claim 17 wherein said data code conversion step is 8-10 GCR encoding and decoding.

Claim 32

The method of claim 17 wherein track format data is generated in said generating track format data step in synchronization with signals from a head drum in said digital storage magnetic tape system.

Claim 33

The method of claim 17 wherein the data is randomized compatible with the DDS standard.

Claim 34

The method of claim 17 wherein the data is interleaved compatible with the DDS standard.

Claim 35

In a digital data storage magnetic tape system for storing data from a host device to magnetic tape having a head drum, a main data buffer coupled to a main data buffer manager coupled to a host device interface, a formatter including a direct memory access controller, the formatter coupled to a frame buffer, and a processor coupled to the main data buffer manager and the formatter, a method of formatting data for accessing and encoding and decoding the data to and from magnetic tape, the data being organized into blocks and including system area data and track format data comprising the operational steps of: (a) transmitting synchronized serial data and clock pulses to the formatter; (b) deserializing the serial data to parallel, (c) computing C1 syndromes from the data; (d) buffer managing including branching on C1 syndrome value being no read errors for zero value and read errors for non-zero value; (e) storing pointers to block with non-zero syndrome values; (f) writing both the data and the syndromes into the frame buffer, thereby constituting a read; (g) reading a complete frame and thereafter reading the non-zero C1 syndrome block pointers for error correction; (h) generating C2 syndromes and pausing when a non-zero syndrome is generated, thereby performing error correction; (i) assembling a frame of data into the frame buffer and correcting all C1 and C2 errors, thereafter moving the data into the main data buffer; and (j) moving the data to the host device interface for communication with the host device.

Claim 36

In a digital data storage magnetic tape system for storing data from a host device to magnetic tape having a head drum, a main data buffer coupled to a main data buffer manager coupled to a host device interface, a formatter including a direct memory access controller, the formatter coupled to a frame buffer, and a processor coupled to the main data buffer manager and the formatter, a method of formatting data for accessing and encoding and decoding the data to and from magnetic tape, the data being organized into blocks and including system area data and track format data comprising the operational steps of: (a) transmitting synchronized serial data and clock pulses to the formatter; (b) deserializing the serial data to parallel, (c) computing C1 syndromes from the data; (d) buffer managing including branching on C1 syndrome value being no read errors for zero value and read errors for non-zero value; (e) storing pointers to block with non-zero syndrome values; (f) writing both the data and the syndromes into the frame buffer, thereby constituting a read; (g) reading a complete frame and thereafter reading the non-zero C1 syndrome block pointers for error correction; (h) generating C2 syndromes and pausing when a non-zero syndrome is generated, thereby performing error correction; (i) assembling a frame of data into the frame buffer and correcting all C1 and C2 errors, thereafter moving the data into the main data buffer; and (j) moving the data to the host device interface for communication with the host device.

Claim 37

The method of claim 28 wherein said C1 syndrome computation step (c) is performed on the fly for main data and sub data as data is moved to and from the tape.

Claim 38

In a processor having an address space, an interrupt register having an address space enable bit and a code bit, and a signal pin for signalling when an instruction byte is fetched, a method of increasing the address space comprising the steps of: creating a first address space utilizing the signal pin and the addressing modes of the address space enable and code bits to designate said first address space; and creating a second address space utilizing the signal pin and the addressing modes the address space enable and code bits to designate said second address space.

Claim 39

In a processor having an address space, an interrupt register having an address space enable bit and a code bit, and a signal pin for signalling when an instruction byte is fetched, a method of increasing the address space comprising the steps of: creating a first address space utilizing the signal pin and the addressing modes of the address space enable and code bits to designate said first address space; and creating a second address space utilizing the signal pin and the addressing modes the address space enable and code bits to designate said second address space.

Claim 40

The method of claim 30 wherein addresses are decoded into said first (CODE) and second (DATA) decoded address spaces as: ______________________________________ Address Space Enable bit Code bit Signal pin Decoded Space ______________________________________ 0 X 0 DATA 0 X 1 CODE 1 0 X DATA 1 1 X CODE. ______________________________________

Claim 41

The method of claim 31 further comprising the step of writing to CODE space to support flash EPROM.

Claim 42

The method of claim 31 further comprising the step of executing from DATA space to support diagnostic firmware routines.

Claim 43

The method of claim 30 wherein said processor is an 80C198 microprocessor.

Claim 44

A formatter for a digital data storage tape system that encodes and decodes data comprising: an interface to a processing unit, said interface coupled to a processor bus; a sequencer, said sequencer coupled to said processor bus and to a read/write channel; and a buffer manager coupled to said interface and to said sequencer by an read/write bus.

Claim 45

A formatter for a digital data storage tape system that encodes and decodes data comprising: an interface to a processing unit, said interface coupled to a processor bus; a sequencer, said sequencer coupled to said processor bus and to a read/write channel; and a buffer manager coupled to said interface and to said sequencer by an read/write bus.

Claim 46

The formatter of claim 35 wherein said interface comprises an address map decoder, ready logic, interrupt control, serial port handshake logic, and a plurality of registers including an interrupt, a serial port address/status, a serial port data, a Galois field value 1, a Galois field value 2, a Galois field result, a Galois square root and a jumper input.

Claim 47

The formatter of claim 35 wherein said sequencer comprises a C1 parity generator, a C1 syndrome generator, a read/write sequencer, an encoder/decoder, an track finding pattern generator, an ID parity and a plurality of registers including a serial/deserializer control 0, a serial/deserializer control 1, a status, two read track checksum, and a bit pointer, a state counter, a block counter and a byte counter.

Claim 48

The formatter of claim 35 wherein said buffer manager comprises a C2 parity generator, a C2 syndrome generator, a data path control, a buffer address generator, a direct memory access arbitrator, a direct memory access handshake, and a randomizer, and a plurality of registers including a direct memory access controller control, SRAM access latch, two track 1 checksum, two track 2 checksum, an ECC control, a control pulse, a C2 block address and a bad C1 block count.