Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
268 words
In a rotary-head digital audio tape system wherein a reproduced digital signal contains audio data, parities P, parities Q, the reproduced digital signal being sequentially written in memory, a code error correction circuit for reading the digital signal from the memory and performing code error correction of the signal by use of the parities P and Q, the code error correction circuit comprising: (a) first means for, during a code error correction using the parities P, reading the whole of the written digital signal from the memory; (b) second means for, during the code error correction using the parities P, performing code error correction of the whole of the digital signal, read from the memory and providing a corrected digital signal; (c) third means for, during the code error correction using the parities P, writing the corrected digital signal into the memory; (d) fourth means for, during a code error correction using the parities Q following the code error correction using the parities P, reading the audio data and the parities Q corresponding to the audio data from the memory without reading the P parities; (e) fifth means for, during the code error correction using the parities Q, performing error correction of the audio data and of the parities Q read by said fourth means while avoiding error correction of the parities P thereby and providing corrected audio data and corrected parities Q, to save time spent in the error correction; and (f) sixth means for, during the code error correction using the parities Q, writing the corrected audio data and the corrected parities Q into the memory.
Claim 2
Dependent Claim
268 words
In a rotary-head digital audio tape system wherein a reproduced digital signal contains audio data, parities P, parities Q, the reproduced digital signal being sequentially written in memory, a code error correction circuit for reading the digital signal from the memory and performing code error correction of the signal by use of the parities P and Q, the code error correction circuit comprising: (a) first means for, during a code error correction using the parities P, reading the whole of the written digital signal from the memory; (b) second means for, during the code error correction using the parities P, performing code error correction of the whole of the digital signal, read from the memory and providing a corrected digital signal; (c) third means for, during the code error correction using the parities P, writing the corrected digital signal into the memory; (d) fourth means for, during a code error correction using the parities Q following the code error correction using the parities P, reading the audio data and the parities Q corresponding to the audio data from the memory without reading the P parities; (e) fifth means for, during the code error correction using the parities Q, performing error correction of the audio data and of the parities Q read by said fourth means while avoiding error correction of the parities P thereby and providing corrected audio data and corrected parities Q, to save time spent in the error correction; and (f) sixth means for, during the code error correction using the parities Q, writing the corrected audio data and the corrected parities Q into the memory.
Claim 3
Dependent Claim
21 words
The code error correction circuit of claim 1 wherein said first and fourth means are composed of an address generation circuit.