US5358884A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual purpose collector contact and isolation scheme for advanced bicmos processes
Assignee: Micron Technology Inc
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Filing: 1992-09-11
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Granted: 1994-10-25
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Expires: 2012-09-11
Abstract
Abstract A scheme and method of fabrication for creating bipolar semiconductor devices with reduced size and greater speed while maintaining device isolation. Using a mesa structure isolated by trenches, collector contact is achieved by a vertical layer of polysilicon surrounding the mesa, deposited within the trench during fabrication.
Inventors
- 👤 Michael P. Violette
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:18
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S148/00; Y10S148/01
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
200 words
A method for fabricating a semiconductor bipolar device for use in an integrated circuit comprising: forming a combination of substantially horizontal layers comprising: a semiconductor substrate layer; a buried layer on top of said substrate, said buried layer doped to form a semiconductor element of a first type; a first surface layer on top of said buried layer; a second surface layer embedded into a section of said first surface layer; an insulating oxide layer on top of said first and second surface layer; etching a trench network into said combination of layers from the top down into the buried layer thereby generating a mesa; depositing a substantially vertical layer of insulating material onto a vertical wall of said mesa; deepening the trench network, thereby exposing the buried layer; implanting an isolating region into a portion of the substrate exposed at a bottom end of the trench network: depositing a substantially vertical layer of polysilicon to exposed layers on said vertical wall of the mesa, filling the trench network with insulating material; creating a first tap to contact the polysilicon layer, a second tap to contact the first surface layer, and a third tap to contact the second surface layer.
Claim 2
Independent Claim
200 words
A method for fabricating a semiconductor bipolar device for use in an integrated circuit comprising: forming a combination of substantially horizontal layers comprising: a semiconductor substrate layer; a buried layer on top of said substrate, said buried layer doped to form a semiconductor element of a first type; a first surface layer on top of said buried layer; a second surface layer embedded into a section of said first surface layer; an insulating oxide layer on top of said first and second surface layer; etching a trench network into said combination of layers from the top down into the buried layer thereby generating a mesa; depositing a substantially vertical layer of insulating material onto a vertical wall of said mesa; deepening the trench network, thereby exposing the buried layer; implanting an isolating region into a portion of the substrate exposed at a bottom end of the trench network: depositing a substantially vertical layer of polysilicon to exposed layers on said vertical wall of the mesa, filling the trench network with insulating material; creating a first tap to contact the polysilicon layer, a second tap to contact the first surface layer, and a third tap to contact the second surface layer.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein said step of forming said first surface layer comprises growing an epitaxial layer.
Claim 4
Dependent Claim
49 words
The method of claim 1, which further comprises: forming a stop layer atop said insulating oxide layer prior to said step of etching a trench network; and polishing the surface of said mesa down to said stop layer, after said step of filling the trench network with insulating material.
Claim 5
Dependent Claim
18 words
The method of claim 3, wherein said step of polishing is performed using a chemical mechanical polishing process.
Claim 6
Dependent Claim
37 words
The method of claim 1, wherein said step of depositing a substantially vertical layer of polysilicon comprises: depositing a coating layer of polysilicon; and anisotropically etching said coating layer, thereby removing horizontal portions of said coating layer.
Claim 7
Dependent Claim
26 words
The method of claim 1, wherein said step of depositing a substantially vertical layer of polysilicon occurs prior to said step of implanting an isolating region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |