US5355463A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit configuration for transforming the logical address space of a processor unit to the physical address space of a memory
Assignee: Quarterhill Inc
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Filing: 1992-01-09
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Granted: 1994-10-11
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Expires: 2012-01-09
Abstract
Abstract A circuit configuration for adapting a logical address space of a processor unit to a physical address space of a memory includes, an interpretation unit, and data and control lines connecting the interpretation unit to the processor unit. The interpretation unit includes a register having a first register region and having a second register region to be written into by the processor unit. The interpretation unit continuously evaluates a logic state of the processor unit, writes contents of the second register region into the first register region at defined logic states and outputs contents of the first register region as an address. A linking unit is connected by address lines to the processor unit, to the interpretation unit and to the memory. The linking unit forms a total address for the memory from addresses transferred by the interpretation unit and the processor unit.
Inventors
- 👤 Udo Moeller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:43
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
173 words
A circuit configuration for transforming a logical address space of a processor unit to a physical address space of a memory, said circuit configuration comprising an interpretation unit; data and control lines for connecting said interpretation unit to said processor unit, said interpretation unit including a register, said register having a first register region and a second register region, said second register region to be written into by said processor unit, said interpretation unit having means for continuously evaluating logic states of said processor unit, for writing contents of said second register region into said first register region at a first one of the logic states and for outputting contents of said first register region as a first address portion; a linking unit, and address lines for connecting said linking unit to said processor unit, to said interpretation unit and to said memory, said linking unit forming a physical address for said memory from the first address portion transferred by said interpretation unit and a second address portion transferred by said processor unit.
Claim 2
Dependent Claim
173 words
A circuit configuration for transforming a logical address space of a processor unit to a physical address space of a memory, said circuit configuration comprising an interpretation unit; data and control lines for connecting said interpretation unit to said processor unit, said interpretation unit including a register, said register having a first register region and a second register region, said second register region to be written into by said processor unit, said interpretation unit having means for continuously evaluating logic states of said processor unit, for writing contents of said second register region into said first register region at a first one of the logic states and for outputting contents of said first register region as a first address portion; a linking unit, and address lines for connecting said linking unit to said processor unit, to said interpretation unit and to said memory, said linking unit forming a physical address for said memory from the first address portion transferred by said interpretation unit and a second address portion transferred by said processor unit.
Claim 3
Dependent Claim
21 words
The circuit configuration according to claim 1, wherein said processor unit has means for reading said register of said interpretation unit.
Claim 4
Dependent Claim
64 words
The circuit configuration according to claim 1, including a stack register connected to said interpretation unit, contents of said first and second register regions being written into said stack register at a second one of the logic states of said processor unit, and said stack register being read out to said first and second register regions at a third one of the logic states.
Claim 5
Dependent Claim
127 words
The circuit configuration according to claim 3, wherein said register of said interpretation unit is a first register, said interpretation unit includes a second register with two further register regions, said two further register regions are written into by said processor unit in each case upon an appearance of a sixth one of the logic states, said second register has a given bit which is set by said processor unit, said interpretation unit has means for selectively reading out said first register region and one of said further register regions at a seventh one of said logic states of said processor unit, in dependence on the state of the given bit, and said second register has a further bit for indicating an overflow of said stack register.
Claim 6
Dependent Claim
57 words
The circuit configuration according to claim 1, wherein said register of said interpretation unit is a first register, and said interpretation unit includes a second register with two further register regions, said two further register regions being written into by said processor unit in each case upon an appearance of a fourth one of the logic states.
Claim 7
Dependent Claim
64 words
The circuit configuration according to claim 5, wherein said second register has a given bit which is set by said processor unit, and said interpretation unit has means for selectively reading out said first register region and one of said further register regions at a fifth one of the logic states of said processor unit, in dependence on the state of the given bit.
Claim 8
Dependent Claim
28 words
The circuit configuration according to claim 1, wherein said interpretation unit places said first and second register regions in a predetermined state, upon resetting of said processor unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |