US4959778A
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US
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Address space switching apparatus
Assignee: Hitachi Ltd
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Filing: 1988-09-30
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Granted: 1990-09-25
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Expires: 2008-09-30
Abstract
Abstract An address space switching apparatus has a group of conventional registers capable of storing address information and a group of additional registers capable of storing address information longer than the address information stored by the group of conventional registers. The register length of the group of additional registers is not restricted by the length of the group of conventional registers and is selected to be of a magnitude sufficient to define a desired operand address space. Information items stored in the group of additional registers such as a base address and an index value associated with the extended address space are selected when an operand address is to be generated so as to be appropriately employed for the address computation, thereby supplying address information having a length sufficient for the extended address space. On the other hand, when an address other than an operand address is to be created, information items stored in the group of conventional registers are selected so as to be utilized in the address computation.
Inventors
- 👤 Hiroo Miyadera
- 👤 Toru Ohtsuki
- 👤 Toshiaki Kawamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
211 words
An address space switching apparatus comprising: address computing means for computing an address; a first group of registers for storing address information; a second group of registers for storing address information that is longer than the address information stored in said first group of registers; selector means controlled by a first control signal for respectively selecting, in response to a first state or a second state of the first control signal, an output from said first group of registers or said second group of registers in order to supply the selected output to said address computing means; means for generating a second control signal indicating a time period during which an operand address is to be generated; means for generating a third control signal indicating whether or not an operand address space is to be extended; and means responsive to the third control signal when the second control signal indicates the time period during which an operand address is to be generated for forcing the first control signal into the second state when the third signal indicates that an operand address space is to be extended and for forcing the first signal into the first state when the third signal indicates that an operand address space is not to be extended.
Claim 2
Dependent Claim
211 words
An address space switching apparatus comprising: address computing means for computing an address; a first group of registers for storing address information; a second group of registers for storing address information that is longer than the address information stored in said first group of registers; selector means controlled by a first control signal for respectively selecting, in response to a first state or a second state of the first control signal, an output from said first group of registers or said second group of registers in order to supply the selected output to said address computing means; means for generating a second control signal indicating a time period during which an operand address is to be generated; means for generating a third control signal indicating whether or not an operand address space is to be extended; and means responsive to the third control signal when the second control signal indicates the time period during which an operand address is to be generated for forcing the first control signal into the second state when the third signal indicates that an operand address space is to be extended and for forcing the first signal into the first state when the third signal indicates that an operand address space is not to be extended.
Claim 3
Dependent Claim
133 words
An address space switching apparatus according to claim 1, further comprising a first control signal generating means for generating the first control signal, said first control signal generating means comprising: means for generating a fourth control signal indicating that one of the first and second groups of registers is to be accessed; and means responsive to the fourth control signal when the second control signal does not indicate the time period during which an operand address is to be generated for forcing the first control signal into the first state when the fourth control signal indicates that said first group of registers is to be accessed and for forcing the first control signal into the second state when the fourth control signal indicates that said second group of registers is to be accessed.
Claim 4
Dependent Claim
27 words
An address space switching apparatus according to claim 2, wherein said first group of registers and said second group of registers are for storing a base address.
Claim 5
Dependent Claim
27 words
An address space switching apparatus according to claim 3, wherein said first group of registers and said second group of registers are for storing an index value.
Claim 6
Dependent Claim
27 words
An address space switching apparatus according to claim 1, wherein said first group of registers and said second group of registers are for storing a base address.
Claim 7
Dependent Claim
27 words
An address space switching apparatus according to claim 5, wherein said first group of registers and said second group of registers are for storing an index value.
Claim 8
Dependent Claim
204 words
An address space switching apparatus for generating an operand address in both a first mode and a second mode, the first mode being a mode during which address expansion is executed and the second mode being a mode during which address expansion is not executed, said address space switching apparatus comprising: address computing means for computing an address; a first group of registers for storing address information; a second group of registers for storing address information that is longer than the address information stored in said first group of registers; selector means controlled by a first control signal for respectively selecting, in response to a first state or a second state of the first control signal, an output from the first group of registers or the second group of registers in order to supply the selected output to said address computing means; mode specifying means for specifying one of the modes; and means responsive to the specified mode for forcing the first signal into the second state when the specified mode represents that an address expansion is to be made and for forcing the first signal into the first state when the specified mode represents that an address expansion is not to be made.
Claim 9
Dependent Claim
204 words
An address space switching apparatus for generating an operand address in both a first mode and a second mode, the first mode being a mode during which address expansion is executed and the second mode being a mode during which address expansion is not executed, said address space switching apparatus comprising: address computing means for computing an address; a first group of registers for storing address information; a second group of registers for storing address information that is longer than the address information stored in said first group of registers; selector means controlled by a first control signal for respectively selecting, in response to a first state or a second state of the first control signal, an output from the first group of registers or the second group of registers in order to supply the selected output to said address computing means; mode specifying means for specifying one of the modes; and means responsive to the specified mode for forcing the first signal into the second state when the specified mode represents that an address expansion is to be made and for forcing the first signal into the first state when the specified mode represents that an address expansion is not to be made.
Claim 10
Dependent Claim
49 words
An address space switching apparatus according to claim 7, further comprising means for generating a second control signal indicating a period of time during which an operand address is to be generated, said first signal being generated by a first signal generating means activated by the second control signal.
Claim 11
Dependent Claim
53 words
An address space switching apparatus according to claim 7, wherein said mode specifying means includes a program status word register for storing a program status word and means for reading a bit that represents the specified mode from the program status word register, the bit constituting a portion of the program status word.
Claim 12
Dependent Claim
198 words
An address space switching apparatus comprising: address computing means for computing an address; a first group of registers, each of the registers of the first group for storing address information; a second group of registers, each of the registers of the second group for storing address information that is longer than the address information stored in each of the registers of the first group; selector means controlled by a first control signal for respectively selecting, in response to a first state or a second state of the first control signal, an output from the first group of registers or the second group of registers in order to supply the selected output to said address computing means; means for generating a second control signal indicating a time period during which an operand address is to be generated; and means for receiving the second control signal and for generating the first control signal, the first control signal being in the second state in a period of time during which an operand address is to be generated and being in the first state during a period of time in which an address other than an operand address is to be generated.
Claim 13
Dependent Claim
198 words
An address space switching apparatus comprising: address computing means for computing an address; a first group of registers, each of the registers of the first group for storing address information; a second group of registers, each of the registers of the second group for storing address information that is longer than the address information stored in each of the registers of the first group; selector means controlled by a first control signal for respectively selecting, in response to a first state or a second state of the first control signal, an output from the first group of registers or the second group of registers in order to supply the selected output to said address computing means; means for generating a second control signal indicating a time period during which an operand address is to be generated; and means for receiving the second control signal and for generating the first control signal, the first control signal being in the second state in a period of time during which an operand address is to be generated and being in the first state during a period of time in which an address other than an operand address is to be generated.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |