Processor data memory address generator

Claim 2

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information.

Claim 3

A processor data memory address generator according to claim 1 wherein said second part of said data address represents the lower order bits of said data address.

Claim 4

A processor data memory address generator according to claim 1 wherein said second part of said data address is formed by consecutive bits of said instruction address.

Claim 5

A processor data memory address generator according to claim 1 wherein said selection information comprises an extent code specifying the variable number e of bits of said second part wherein e is an integer greater than or equal to zero and less than b.

Claim 6

A processor data memory address generator according to claim 4 further comprising a first group of m multiplexers, where m is equal to the largest possible value of the variable number e, each of said multiplexers receiving on a first input a selected bit of said location information and on a second input a selected bit of said instruction address, and wherein the nth multiplexer, for any value of n between 1 and m, inclusive, provides as an output, the signal applied to a first input if n is greater than e or the signal applied to a second input otherwise, said second part of the data address being established on the basis of the output signals of said multiplexers of order e or lower and said first part of said address being established on the basis of the non-selected bits of said location information and the output signals of said multiplexers of order greater than e.

Claim 7

A processor data memory address generator according to claim 5 further comprising a decoder producing from said extent code selection signals to control said multiplexers.

Claim 8

A processor data memory address generator according to claim 5 wherein an indexing set comprises at least some of the bits of said instruction address each assigned an order number, and wherein said selection information further comprises an operation code specifying an order f greater than zero, indicating that said second part of the data address is made up of e bits of said indexing set of order numbers from f to f+e-1.

Claim 9

A processor data memory address generator according to claim 7 further comprising a second group of m multiplexers of which the nth multiplexer, for any value of n between 1 and m, inclusive, receives on an input of order number k, where k is greater than or equal to 1, the bit of order number (n+k-1) of said indexing set, and has an output connected to the second input of the nth multiplexer of said first group of m multiplexers, wherein all the multiplexers of said second group provide as an output, the signal applied to their input of order number f by means of said operation code.

Claim 10

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information to increment said data address during the repetition of a loop of 2 p instructions, the second part of the data address being incremented by one unit each time said loop is executed and being made up of e bits of the instruction address form order p to p+e-1, where p is greater than zero, and e is greater than or equal to zero.

Claim 11

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information to increment said data address during the repetition of a loop of 2 p instructions, the second part of the data address being incremented by one unit each time said loop is executed and being made up of e bits of the instruction address form order p to p+e-1, where p is greater than zero, and e is greater than or equal to zero.

Claim 12

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information to modularly change said data address during the repetition of a loop of 2 p instructions, the second part of the data address being incremented by 2 q units on each execution of said loop where q is less than p, and comprising e bits of the instruction address from order (p-q) to p-q+e-1, where p is greater than zero, and e and q are greater than or equal to zero.

Claim 13

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information to modularly change said data address during the repetition of a loop of 2 p instructions, the second part of the data address being incremented by 2 q units on each execution of said loop where q is less than p, and comprising e bits of the instruction address from order (p-q) to p-q+e-1, where p is greater than zero, and e and q are greater than or equal to zero.

Claim 14

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected sets of bits being identified by said selection information to circularly increment said data address during the repetition of a loop of 2 p instruction r times, the second part of the data address being equal to the number of executions of said loop already done modulo a specific number 2 s , r being the product of an integer u and 2 s , said second part comprising s bits of the instruction address of order p to (p+s-1), where p is greater than zero, and s is greater than or equal to zero.

Claim 15

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected sets of bits being identified by said selection information to circularly increment said data address during the repetition of a loop of 2 p instruction r times, the second part of the data address being equal to the number of executions of said loop already done modulo a specific number 2 s , r being the product of an integer u and 2 s , said second part comprising s bits of the instruction address of order p to (p+s-1), where p is greater than zero, and s is greater than or equal to zero.

Claim 16

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information by circulary modularly change said data address during the repetition of a loop of 2 p instruction r times, the second part of the data address being the product of a number 2 q and the number of executions of said loop already done modulo a particular number 2 s , q being less than p, and r being the product of an integer u and 2 s , said second part comprising s bits of the instruction address of order (p-q) to (p-q+e-1), where p is greater than zero, and s and q are greater than or equal to zero.

Claim 17

A processor data memory address generator receiving an instruction address from an instruction counter and a control word from a program controller which receives instructions from a program memory addressed by said instruction counter, said program controller producing a program signal addressed to an arithmetic and logic unit, said instruction counter being incremented by a clock signal and reset by said program controller, wherein said control word comprises location information and selection information and said address generator comprises means for producing a data address b bits in length having a first part comprising bits of said location information and a second part formed by a selected set of bits of the instruction address, said selected set of bits being identified by said selection information by circulary modularly change said data address during the repetition of a loop of 2 p instruction r times, the second part of the data address being the product of a number 2 q and the number of executions of said loop already done modulo a particular number 2 s , q being less than p, and r being the product of an integer u and 2 s , said second part comprising s bits of the instruction address of order (p-q) to (p-q+e-1), where p is greater than zero, and s and q are greater than or equal to zero.