Shift register circuit with three-input nor gates in selector circuit

Claim 2

A shift register circuit comprising a selector circuit for selecting one of two input signals and a flip-flop circuit connected to said selector circuit and synchronized with a clock signal having a prescribed period, said flip-flop circuit for latching the selected signal, said selector circuit comprising: a first two-input NOR circuit to which a first data signal and a selection signal are input; a second two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the selection signal are input; a third two-input NOR circuit to which a second data signal and a reverse selection signal having an opposite phase from the selection signal are input; a fourth two-input NOR circuit to which a second reverse data signal having an opposite phase from the second data signal and the reverse selection signal are input; a first three-input NOR circuit to which output signals from said first and third two-input NOR circuits and the clock signal are input; and a second three-input NOR circuit to which output signals from said second and fourth two-input NOR circuits and the clock signal are input.

Claim 3

A shift register circuit comprising a selector circuit for selecting one of two input signals and a flip-flop circuit connected to said selector circuit and synchronized with a clock signal having a prescribed period, said flip-flop circuit for latching the selected signal, said selector circuit comprising: a first two-input NOR circuit to which a clock signal and a reverse selection signal having an opposite phase from a selection signal are input; a first inverter to which an output signal from said first two-input NOR circuit is input; a second two-input NOR circuit to which the clock signal and the selection signal are input; a second inverter to which an output signal from said second two-input NOR circuit is input; a third two-input NOR circuit to which a first data signal and an output signal from said first inverter are input; an fourth two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the output signal from said first inverter are input; a fifth two-input NOR circuit to which a second data signal and an output signal from said second inverter are input; a sixth two-input NOR circuit to which a second reverse data signal having an opposite phase from the second data signal and the output signal from said second inverter are input; a first three-input NOR circuit to which output signals from said third and fifth two-input NOR circuits are input; and a second three-input NOR circuit to which output signals from said fourth and sixth two-input NOR circuits are input, an output from said first three-input NOR circuit being connected to an input of said second three-input NOR circuit and an output from said second three-input NOR circuit being connected to an input of said first three-input NOR circuit.

Claim 4

A shift register circuit comprising a selector circuit for selecting one of two input signals and a flip-flop circuit connected to said selector circuit and synchronized with a clock signal having a prescribed period, said flip-flop circuit for latching the selected signal, said selector circuit comprising: a first two-input NOR circuit to which a clock signal and a reverse selection signal having an opposite phase from a selection signal are input; a first inverter to which an output signal from said first two-input NOR circuit is input; a second two-input NOR circuit to which the clock signal and the selection signal are input; a second inverter to which an output signal from said second two-input NOR circuit is input; a third two-input NOR circuit to which a first data signal and an output signal from said first inverter are input; an fourth two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the output signal from said first inverter are input; a fifth two-input NOR circuit to which a second data signal and an output signal from said second inverter are input; a sixth two-input NOR circuit to which a second reverse data signal having an opposite phase from the second data signal and the output signal from said second inverter are input; a first three-input NOR circuit to which output signals from said third and fifth two-input NOR circuits are input; and a second three-input NOR circuit to which output signals from said fourth and sixth two-input NOR circuits are input, an output from said first three-input NOR circuit being connected to an input of said second three-input NOR circuit and an output from said second three-input NOR circuit being connected to an input of said first three-input NOR circuit.

Claim 5

The shift register circuit of claim 1 wherein said flip-flop circuit is a master-slave flip-flop circuit including a master stage and said first and second three-input NOR circuits also serve as switching gates of the master stage of the master-slave flip-flop circuit.

Claim 6

The shift register circuit of claim 2 wherein said flip-flop circuit is a master-slave flip-flop circuit including a master stage and a slave stage and said first and second three-input NOR circuits also serve as switching gates of the master stage of the master-slave flip-flop circuit.

Claim 7

The shift register circuit of claim 4 comprising delay means for delaying a reverse clock signal having opposite phase from the clock signal and supplying the delayed reverse clock signal to a switching gate of said slave stage of said master-slave flip-flop circuit, the reverse clock signal being delayed by a time interval equivalent to a time the clock signal is delayed by one of (i) said first two-input NOR circuit and said first inverter and (ii) said second two-input NOR circuit and said second inverter.