Fault judging device comprising a compression circuit for compressing output pattern signals of a circuit model

Claim 1

A fault judging device for use in simulating a circuit model which is defined by a fault data signal indicative of one of circuit elements in said circuit model to produce a judging result signal, said circuit model being operable in response to first through n-th input pattern signals and producing first through n-th output pattern signals where n represents a natural number greater than unity, said device comprising: signal producing means connected to said circuit model for producing said fault data signal for selectively enabling said one of the circuit elements; a compression circuit connected to said circuit model for compressing said first through said n-th output pattern signals by cyclic coding to produce a compressed signal represented by a cyclic code sequence; a cyclic code memory for memorizing a specific cyclic code sequence which defines a normal circuit related to said circuit model; and comparing means connected to said compression circuit and said cyclic code memory for comparing said cyclic code sequence with said specific cyclic code sequence, said comparing means producing a comparison result signal, as said judging result signal, representative of a fault of said one of the circuit elements when said cyclic code sequence does not coincide with said specific cyclic code sequence.