US5350706A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS memory cell array
Assignee: Texas Instruments Inc
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Filing: 1992-09-30
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Granted: 1994-09-27
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Expires: 2012-09-30
Abstract
Abstract A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
Inventors
- 👤 Dave J. McElroy
- 👤 Manzur Gill
- 👤 Pradeep L. Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:07
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
154 words
A method of fabricating rows and columns of CMOS memory cells in an array on a semiconductor substrate having a first conductivity type, said array having source lines parallel to said rows of cells, comprising the steps of: forming a column-photoresist pattern on the semiconductor surface to define field oxide isolation regions between areas where said columns of cells are to be formed; implanting a dopant of said first conductivity-type in areas not covered by said column-photoresist pattern to form a channel stop region; removing said column-photoresist pattern; forming a row-photoresist pattern on the semiconductor surface to define said source lines for connecting the sources of rows of said cells to be formed; implanting said source lines with a dopant of a second conductivity-type opposite said first conductivity-type along areas not covered by said row-photoresist pattern; removing said row-photoresist pattern; and then growing an oxide layer for isolation in said field oxide isolation regions.
Claim 2
Independent Claim
154 words
A method of fabricating rows and columns of CMOS memory cells in an array on a semiconductor substrate having a first conductivity type, said array having source lines parallel to said rows of cells, comprising the steps of: forming a column-photoresist pattern on the semiconductor surface to define field oxide isolation regions between areas where said columns of cells are to be formed; implanting a dopant of said first conductivity-type in areas not covered by said column-photoresist pattern to form a channel stop region; removing said column-photoresist pattern; forming a row-photoresist pattern on the semiconductor surface to define said source lines for connecting the sources of rows of said cells to be formed; implanting said source lines with a dopant of a second conductivity-type opposite said first conductivity-type along areas not covered by said row-photoresist pattern; removing said row-photoresist pattern; and then growing an oxide layer for isolation in said field oxide isolation regions.
Claim 3
Dependent Claim
41 words
The method of claim 1, wherein said step of fabricating a column-photoresist pattern is performed before said steps of fabricating a row-photoresist pattern and implanting said source lines, such that said source lines are implanted through portions of said column-photoresist pattern.
Claim 4
Dependent Claim
29 words
The method of claim 1, wherein said steps of fabricating said row-photoresist pattern and of implanting said source lines are performed before said step of fabricating said column-photoresist pattern.
Claim 5
Dependent Claim
56 words
The method of claim 1, wherein said step of fabricating a column-photoresist pattern comprises the substeps of depositing a resist layer, exposing and developing said resist layer to define said column-photoresist pattern, and etching said resist layer to define said column-photoresist pattern, and etching said resist layer to remove areas not covered by said column-photoresist pattern.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein said dopant of said second conductivity-type is an n-type doping agent.
Claim 7
Dependent Claim
25 words
The method of claim 1, wherein said growing the oxide layer in said field oxide regions is performed by means of a localized oxidation process.
Claim 8
Dependent Claim
29 words
The method of claim 1, and further comprising the steps of oxidizing said source lines at the same time as growing the oxide layer in said field oxide regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-26 | 1998-03-28 | 1998-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-26 | 2002-03-28 | 2002-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-26 | 2006-03-28 | 2006-09-27 | $7700.00 | Window Closed / Lapsed |