Semiconductor memory device

Claim 2

A semiconductor memory device of this embodiment includes: a plurality of memory cells for storing data; at least one redundant block having strings of the memory cells arranged in a predetermined direction; and a plurality of regular blocks having strings of the memory cells arranged in the predetermined direction, wherein, when there is a faulty block among the regular blocks, the redundant block is used instead of the faulty block, and wherein each string of the memory cells in the regular blocks includes: a pair of bit lines, connected to a plurality of the memory cells, for transmitting signals read out from the memory cells and signals to write data in the memory cells; first pull-up switching means for starting or stopping pulling-up of the bit lines; and second pull-up switching means for starting or stopping pulling-up of the bit lines to prevent data stored in the memory cells from being lost, said semiconductor memory device further comprising: first driving means for driving said first pull-up switching means so that said first pull-up switching means in a faulty regular block is always turned off, and that said first pull-up switching means in a normal regular block is turned on in a standby state and is turned off when reading or writing data; and second driving means for driving said second pull-up switching means so that said second pull-up switching means in a faulty regular block is always turned off, and that said second pull-up switching means in a selected string of the memory cells in a normal regular block is turned off and said second pull-up switching means in an unselected string of the memory cells in the normal regular block is turned on when reading or writing data.

Claim 3

The semiconductor memory device according to claim 1, wherein said first pull-up switching means includes: a power supply line having a high state; and a first switching element, located between said power supply line and said bit lines, for connecting or disconnecting the power supply line and the bit lines.

Claim 4

The semiconductor memory device according to claim 2, wherein said first pull-up switching means further includes: a second switching element, located between the pair of bit lines, for connecting or disconnecting the bit lines.

Claim 5

The semiconductor memory device according to claim 3, wherein said first switching element and said second switching element are transistors.

Claim 6

The semiconductor memory device according to claim 1, wherein said second pull-up switching means includes: a high state of a power supply line; and a third switching element, located between the power supply line and the bit lines, for connecting or disconnecting the power supply line and the bit lines.

Claim 7

The semiconductor memory device according to claim 5, wherein said third switching element is a transistor.

Claim 8

The semiconductor memory device according to claim 1, further comprising: bit-line pull-up timing signal outputting means for transmitting to each block a bit-line pull-up timing signal which has different states in a standby state and in an operation; and redundant-block enable signal outputting means for transmitting to each block a redundant-block enable signal which has different states depending on whether a target block to which the signal is transmitted has a fault, wherein said first driving means includes first drive-signal generating means, provided in each regular block, for generating a first drive signal to drive said first pull-up switching means based on the bit-line pull-up timing signal and the redundant-block enable signal.

Claim 9

The semiconductor memory device according to claim 7, wherein the bit-line pull-up timing signal becomes a first level when said device is on standby, and becomes a second level when said device operates, the redundant-block enable signal becomes the first level when a target block to Which the redundant-block enable signal is to be output has no fault, and becomes the second level when the target block has a fault, and wherein said first drive-signal generating means is a first logic circuit which outputs the second level of the first drive signal only when both of the bit-line pull-up timing signal and the redundant-block enable signal have the first level.

Claim 10

The semiconductor memory device according to claim 8, wherein the first level corresponds to a low state, and the second level corresponds to a high state, and wherein said first logic circuit is a positive logic NOR circuit.

Claim 11

The semiconductor memory device according to claim 1, further comprising: redundant-block enable signal outputting means for transmitting to each block a redundant-block enable signal which has different states depending on whether a target block to which the redundant-block enable signal is to be transmitted has a fault, wherein each string of the memory cells includes timing signal outputting means for outputting a timing signal which has different states depending on whether the string of the memory cells is selected or not; and wherein said second driving means includes second drive-signal generating means for generating a second drive signal for driving said second pull-up switching means depending on the redundant-block enable signal and the timing signal, said second drive-signal generating means being provided in each string of the memory cells.

Claim 12

The semiconductor memory device according to claim 10, wherein the redundant-block enable signal becomes a first level when the target block has no fault and goes into a second stage when the target block has a fault, and the timing signal becomes the first level when the target string of the memory cells is selected, and becomes the second level when the target string of the memory cells is not selected, and wherein said second drive-signal generating means is a second logic circuit which transmits the second level of the second drive signal only when the first level of the redundant-block enable signal and the second level of the timing signal are output.

Claim 13

The semiconductor memory device according to claim 11, wherein the first level corresponds to a low state, and the second level corresponds to a high state, and wherein said second logic circuit is a positive logic INHIBIT NAND circuit.

Claim 14

The semiconductor memory device according to claim 1, wherein each of the memory cells is of a static type including two access transistors, two drive transistors and two load elements.

Claim 15

The semiconductor memory device according to claim 13, wherein said load elements are load transistors.

Claim 16

The semiconductor memory device according to claim 13, wherein said load elements are load resistors.

Claim 17

The semiconductor memory device according to claim 13, wherein said load elements are load thin-film transistors.

Claim 18

The semiconductor memory device according to claim 13, wherein said second pull-up switching means includes: a high state of a power supply line; a pull-up transistor, located between the power supply line and the bit lines, for connecting or disconnecting the power supply line and the bit lines, said pull-up transistor having a driving power lower than than that of said drive transistors in the memory cells.

Claim 19

A semiconductor memory device of this embodiment includes: a plurality of memory cells for storing data; at least one redundant block having strings of the memory cells arranged in a predetermined direction; and a plurality of regular blocks having strings of the memory cells arranged in the predetermined direction, wherein, when there is a faulty block among the regular blocks, the redundant block is used instead of the faulty block, and wherein each string of the memory cells in the regular blocks includes: a pair of bit lines, connected to a plurality of the memory cells, for transmitting signals read from the memory cells and signals to write data in the memory cells; first pull-up switching means for starting or stopping pulling up the bit lines; and second pull-up switching means for starting or stopping pulling-up of the bit lines to prevent data stored in the memory cells from being lost, said semiconductor memory device further comprising: first driving means for driving said first pull-up switching means so that said first pull-up switching means in a faulty regular block is always turned off, and that said first pull-up switching means in a normal regular block is turned on in a standby state and is turned off when reading or writing data; and second driving means for driving said second pull-up switching means so that said second pull-up switching means in a faulty regular block is always turned off, said second pull-up switching means in a normal block regular block is turned off in the standby state and when reading out data, and that said second pull-up switching means in a selected normal regular block is turned on and said second pull-up switching means in an unselected normal regular block is turned off when writing data.

Claim 20

A semiconductor memory device of this embodiment includes: a plurality of memory cells for storing data; at least one redundant block having strings of the memory cells arranged in a predetermined direction; and a plurality of regular blocks having strings of the memory cells arranged in the predetermined direction, wherein, when there is a faulty block among the regular blocks, the redundant block is used instead of the faulty block, and wherein each string of the memory cells in the regular blocks includes: a pair of bit lines, connected to a plurality of the memory cells, for transmitting signals read from the memory cells and signals to write data in the memory cells; first pull-up switching means for starting or stopping pulling up the bit lines; and second pull-up switching means for starting or stopping pulling-up of the bit lines to prevent data stored in the memory cells from being lost, said semiconductor memory device further comprising: first driving means for driving said first pull-up switching means so that said first pull-up switching means in a faulty regular block is always turned off, and that said first pull-up switching means in a normal regular block is turned on in a standby state and is turned off when reading or writing data; and second driving means for driving said second pull-up switching means so that said second pull-up switching means in a faulty regular block is always turned off, said second pull-up switching means in a normal block regular block is turned off in the standby state and when reading out data, and that said second pull-up switching means in a selected normal regular block is turned on and said second pull-up switching means in an unselected normal regular block is turned off when writing data.

Claim 21

The semiconductor memory device according to claim 18, wherein said first pull-up switching means includes: a power supply line having a high state; and a first switching element, located between the power supply line and the bit lines, for connecting the power supply line to the bit lines and disconnecting the power supply line from the bit lines.

Claim 22

The semiconductor memory device according to claim 19, wherein said first pull-up switching means further includes: a second switching element, located between said pair of bit lines, for connecting or disconnecting the bit lines.

Claim 23

The semiconductor memory device according to claim 20, wherein said first switching element and said second switching element are transistors.

Claim 24

The semiconductor memory device according to claim 18, wherein said second pull-up switching means includes: a power supply line having a high state; and a third switching element, located between the power supply line and the bit lines, for connecting or disconnecting the power supply line and the bit lines.

Claim 25

The semiconductor memory device according to claim 22, wherein said third switching element is a transistor.

Claim 26

The semiconductor memory device according to claim 18, further comprising: bit-line pull-up timing signal outputting means for transmitting to each block a bit-line pull-up timing signal of different states in a standby state and in an operation; and redundant-block enable signal outputting means for transmitting to each block a redundant-block enable signal which has different states depending on whether a target block to which the signal is to be transmitted has a fault, wherein said first driving means includes first drive-signal generating means, provided in each regular block, for generating a first drive signal to drive said first pull-up switching means according to the bit-line pull-up timing signal and the redundant-block enable signal.

Claim 27

The semiconductor memory device according to claim 24, wherein the bit-line pull-up timing signal becomes a first level when said device is on standby, and becomes a second level when said device operates, the redundant-block enable signal becomes the first level when a target block to which the redundant-block enable signal is to be transmitted has no fault, and becomes the second level when the target block has a fault, and wherein said first drive-signal generating means is a first logic circuit which outputs the second level of the first drive signal only when both of the bit-line pull-up timing signal and the redundant-block enable signal have the first level.

Claim 28

The semiconductor memory device according to claim 25, wherein the first level corresponds to a low state, and the second level corresponds to a high state, and wherein said first logic circuit is a positive logic NOR circuit.

Claim 29

The semiconductor memory device according to claim 18, further comprising: redundant-block enable signal outputting means for transmitting to each block a redundant-block enable signal which has different states depending on whether a target block to which the redundant-block enable signal is to be transmitted has a fault; block-address outputting means for outputting to each block a block address for selecting a block; write-signal outputting means for transmitting to each block a write signal which has different states depending on whether a write operation is performed, wherein said second driving means includes second drive-signal generating means for generating a second drive signal for driving said second pull-up switching means depending on the redundant-block enable signal, the block address and the write signal, said second drive-signal generating means being provided in each regular block.

Claim 30

The semiconductor memory device according to claim 27, wherein the redundant-block enable signal becomes a first level when the target block has no fault and becomes a second level when the target block has a fault, and the write signal becomes the second level when performing a write operation, and becomes the first level when the write operation is not performed, and wherein said second drive-signal generating means includes: a third logic circuit which receives the block address and outputs the first level of a block selection sub-signal when its own block address is input and outputs the second level of the block selection sub-signal when a block address other than its own block address is input; a fourth logic circuit which receives the redundant-block enable signal and the block selection sub-signal, and outputs the second level of the block selection signal only when the both of the input signals have the first level; and a fifth logic circuit which receives receives the write signal and the block selection signal, and outputs the second level of the second drive signal only when both of the input signals have the second level.

Claim 31

The semiconductor memory device according to claim 28, wherein the first level corresponds to a low state, and the second level corresponds to a high state, and wherein said third logic circuit is a positive logic programmable NAND circuit, said fourth logic circuit is a positive logic NOR circuit, and said fifth logic circuit is a positive logic NOR circuit.

Claim 32

The semiconductor memory device according to claim 18, wherein each of the memory cells is of a static type including two access transistors, two drive transistors and two load elements.

Claim 33

The semiconductor memory device according claim 30, wherein said load elements are load transistors.

Claim 34

The semiconductor memory device according to claim 30, wherein said load elements are load resistors.

Claim 35

The semiconductor memory device according to claim 30, wherein said load elements are load thin-film transistors.

Claim 36

The semiconductor memory device according to claim 30, wherein said second pull-up switching means includes: a high state of a power supply line; and a pull-up transistor, located between the power supply line and the bit lines, for connecting or disconnecting the power supply line and the bit lines, said pull-up transistor having a driving power lower than that of said drive transistors in the memory cells.

Claim 37

The semiconductor memory device according to claim 18, further comprising a write driver for transmitting to the bit lines a data signal for writing data in the memory cells, wherein said second pull-up switching means includes: a high state of a power supply line; and a pull-up transistor, located between the power supply line and the bit lines, for connecting or disconnecting the power supply line and the bit lines, and wherein said write driver includes a transistor for starting or stopping the outputting of the data signal, said transistor in said write driver having a driving power greater than that of said pull-up transistor so as to enable writing of data.