Semiconductor memory device

Claim 1

A static semiconductor memory device comprising: a row address decoder supplied with a row address for decoding the row address; a column address decoder supplied with a column address for decoding the column address; a plurality of columns each constituted by a bit line pair; a plurality of static memory cell grups each coupled to a corresponding one of bit line pairs constituting said columns, said static memory cell groups respectively comprising a plurality of static memory cells, column transfer gate means coupled to each of said bit line pairs for selecting a specific column out of said columns responsive to a decoded output of said column address decoder; a plurality of word lines each coupled to a corresponding one of said static memory cells in each of said bit line pairs; word line driver means coupled to said word lines for driving a selected word line out of said word lines responsive to a decoded output of said row address decoder; a pair of data buses coupled to each of said bit line pairs via said column transfer gate means; an input/output circuit for entering a write-in data which is to be written into a selected static memory cell and for outputting a read-out data read out from a selected static memory cell and obtained via said pair of data buses; a write circuit coupled to said pair of data buses and a high potential power supply line, for driving said data buses complementarily in accordance with the write-in data to be written into the selected static memory cell designated by the row and column addresses; and a clamp circuit connected between said write circuit and a low potential power supply line, for clamping one of the two data buses which has the lower potential during a write-in operation.