Patent US5349310A successfully refreshed from Google Patents.
US5349310A
Expired / Lapsed
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Digitally controlled fractional frequency synthesizer
Assignee: Xylon LLC
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Filing: 1993-06-09
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Granted: 1994-09-20
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Expires: 2013-06-09
Abstract
Abstract The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.
Inventors
- 👤 Klaus-Hartwig Rieder
- 👤 Gunter Horsch
- 👤 William E. Powell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:57
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976; H03L7/1978; H03L7/1806; H03L7/183; H03L7/185
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
101 words
A controllable oscillator, comprising a fixed frequency generator (1) connected to a frequency divider (2) with an adjustable divider ratio, wherein the output of the frequency divider (2) is connected to the input of a phase detector of an analog phase control circuit (3), wherein the frequency divider (2) comprises a register, whose output is connected to a first input of an adder, wherein a second input of the adder is connected to a microprocessor (OBC), and wherein an output of the adder is connected to a nominal frequency input of the phase detector of the analog phase control circuit (3).
Claim 2
Dependent Claim
101 words
A controllable oscillator, comprising a fixed frequency generator (1) connected to a frequency divider (2) with an adjustable divider ratio, wherein the output of the frequency divider (2) is connected to the input of a phase detector of an analog phase control circuit (3), wherein the frequency divider (2) comprises a register, whose output is connected to a first input of an adder, wherein a second input of the adder is connected to a microprocessor (OBC), and wherein an output of the adder is connected to a nominal frequency input of the phase detector of the analog phase control circuit (3).
Claim 3
Dependent Claim
86 words
The controllable oscillator of claim 1, wherein the output of the adder is connected to a first input of a cycle stealing circuit, wherein a second input of the cycle stealing circuit is connected to the output of the fixed frequency generator (1), and wherein a frequency divider with a fixed divider ratio is connected to an output of the cycle stealing circuit and wherein an output of the divider with a fixed divider ratio is connected to the nominal frequency input of the phase detector.
Claim 4
Dependent Claim
151 words
The controllable oscillator of claim 1, wherein the fixed frequency generator (1) is connected on the one hand to the register by a frequency divider with a fixed divider ratio, and on the other is switched through a first cycle stealing circuit, which forms a difference between the frequency of the fixed frequency generator (1) and the frequency of the adder's output pulses, and provides the difference to the nominal frequency input of the phase detector in the analog phase control circuit (3), by means of a downstream frequency divider, and wherein the output of the adder is connected through a second cycle stealing circuit, which forms the difference between the frequency of the adder's output pulses and the output frequency of the analog phase control circuit (3), to the comparison frequency input of the phase detector in the analog phase control circuit (3), by means of a downstream frequency divider.
Claim 5
Dependent Claim
195 words
A controllable oscillator, comprising a fixed frequency generator (1) connected to a frequency divider (2) with a dynamically controlled divider ratio, wherein the output of the frequency divider (2) is connected to the input of a phase detector of an analog phase control circuit (3), wherein the fixed frequency generator (1) is connected to the nominal frequency input of the phase detector through a frequency divider, wherein the input of the frequency divider (2) with a dynamically controlled divider ratio is connected to the output of the analog phase control circuit (3), and wherein the output of the frequency divider (2) with a dynamically controlled divider ratio is connected to the comparison frequency input of the phase detector in analog phase control circuit (3), wherein the frequency divider with a dynamically controlled divider ratio comprises an adder having one input connected to a register and another input to a signal processor, the adder having one output connected to an input of the register and a carry output of the adder used as the output of the frequency divider (2) and wherein the fixed frequency generator (1) is connected to a clock input of the register.
Claim 6
Dependent Claim
195 words
A controllable oscillator, comprising a fixed frequency generator (1) connected to a frequency divider (2) with a dynamically controlled divider ratio, wherein the output of the frequency divider (2) is connected to the input of a phase detector of an analog phase control circuit (3), wherein the fixed frequency generator (1) is connected to the nominal frequency input of the phase detector through a frequency divider, wherein the input of the frequency divider (2) with a dynamically controlled divider ratio is connected to the output of the analog phase control circuit (3), and wherein the output of the frequency divider (2) with a dynamically controlled divider ratio is connected to the comparison frequency input of the phase detector in analog phase control circuit (3), wherein the frequency divider with a dynamically controlled divider ratio comprises an adder having one input connected to a register and another input to a signal processor, the adder having one output connected to an input of the register and a carry output of the adder used as the output of the frequency divider (2) and wherein the fixed frequency generator (1) is connected to a clock input of the register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |