Patent US5347648A successfully refreshed from Google Patents.
US5347648A
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Ensuring write ordering under writeback cache error conditions
Assignee: Valiant Corp
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Filing: 1992-07-15
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Granted: 1994-09-13
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Expires: 2012-07-15
Abstract
Abstract Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that provides limited use of the data in the cache; a read or write request for data not owned in the cache is made to the main memory instead of the cache, even when the data is valid in the cache, although owned data is read from the cache. In ETM, when the processor makes a first write request to data not owned in the cache followed by a second write request to data owned in the cache, write data of the first write request is prevented from being received by the main memory after write data of the second request while permitting writeback of the data owned by the cache. Preferably this is done by sending the write requests from the processor through the non-writeback queue, and when a write request accesses data in a block of data owned by the cache, disowning the block of data in the cache and writing the disowned block of data back to the main memory.
Inventors
- 👤 Rebecca L. Stamm
- 👤 Ruth I. Bahar
- 👤 Raymond L. Strouble
- 👤 Nicholas D. Wade
- 👤 John H. Edmondson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0811; G06F12/0815; G06F12/0831; G06F9/3854; G06F9/3858; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/025; G06F2212/00; G06F2212/10; G06F2212/1032
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
283 words
A method of operating a digital computer system having a processor and a cache memory, and a main memory, said method comprising the steps of: storing ownership information in association with blocks of data in said cache memory, said ownership information indicating whether said cache memory owns each block of data stored in said cache memory; sending writeback transactions from said processor and cache memory through a writeback queue to said main memory, and sending non-writeback transactions from said processor and cache memory through a non-writeback queue to said main memory; accessing data in said cache memory, and upon finding error in the data accessed in said cache memory, entering an error transition mode to provide limited use of data in said cache, wherein said method during said error transition mode includes a) when said processor makes a memory access request for data not owned in said cache memory, making a memory access to said main memory instead of said cache memory, even when said memory access request is for data in a block of data in said cache memory; b) when said processor makes a memory read request for data owned by said cache memory, making a read access to said cache memory; and c) when said processor makes a first memory write request to a block of data not owned in said cache memory followed by a second memory write request to a block of data owned in said cache memory, preventing write data of said first memory write request from being received by said main memory after write data of said second memory write request while permitting writeback of data from said block of data owned in said cache memory.
Claim 2
Independent Claim
283 words
A method of operating a digital computer system having a processor and a cache memory, and a main memory, said method comprising the steps of: storing ownership information in association with blocks of data in said cache memory, said ownership information indicating whether said cache memory owns each block of data stored in said cache memory; sending writeback transactions from said processor and cache memory through a writeback queue to said main memory, and sending non-writeback transactions from said processor and cache memory through a non-writeback queue to said main memory; accessing data in said cache memory, and upon finding error in the data accessed in said cache memory, entering an error transition mode to provide limited use of data in said cache, wherein said method during said error transition mode includes a) when said processor makes a memory access request for data not owned in said cache memory, making a memory access to said main memory instead of said cache memory, even when said memory access request is for data in a block of data in said cache memory; b) when said processor makes a memory read request for data owned by said cache memory, making a read access to said cache memory; and c) when said processor makes a first memory write request to a block of data not owned in said cache memory followed by a second memory write request to a block of data owned in said cache memory, preventing write data of said first memory write request from being received by said main memory after write data of said second memory write request while permitting writeback of data from said block of data owned in said cache memory.
Claim 3
Dependent Claim
47 words
The method as claimed in claim 1, which includes sending the write data of said first memory write request through said non-writeback queue to said main memory, and then sending the write data of said second memory write request through said non-writeback queue to said main memory.
Claim 4
Dependent Claim
38 words
The method as claimed in claim 2, which includes sending a writeback of said block of data owned in said cache memory through said writeback queue to said main memory in response to said second memory write request.
Claim 5
Dependent Claim
64 words
The method as claimed in claim 3, wherein said main memory receives said write data of said second memory write request before said writeback of said block of data owned by said cache memory, and waits for receipt of said writeback of said block of data owned in said cache memory before writing to memory said write data of said second memory write request.
Claim 6
Dependent Claim
37 words
The method as claimed in claim 3, which includes changing said ownership information in said cache memory to indicate that said block of data owned by said cache memory is no longer owned by said cache memory.
Claim 7
Dependent Claim
38 words
The method as claimed in claim 1, which includes sending a writeback of said block of data owned in said cache memory through said writeback queue to said main memory in response to said second memory write request.
Claim 8
Dependent Claim
30 words
The method as claimed in claim 6, wherein said write data of said second write request is included in the writeback of said block of data owned by said cache.
Claim 9
Dependent Claim
71 words
The method as claimed in claim 7, which includes sending write data of said first memory write request through said non-writeback queue to said main memory, and selecting priority between removal from said writeback queue and removal from said non-writeback queue so that said write data of said first write request is removed from said non-writeback queue before write data of said second write request is removed from said writeback queue.
Claim 10
Dependent Claim
47 words
The method as claimed in claim 8, wherein removal from said writeback queue is given priority over removal from said non-writeback queue unless said non-writeback queue includes write data loaded into said non-writeback queue before all writebacks in said writeback queue were loaded into said writeback queue.
Claim 11
Dependent Claim
27 words
The method as claimed in claim 9, which includes setting write order conflict bits in said non-writeback queue when a writeback is loaded in said writeback queue.
Claim 12
Dependent Claim
26 words
The method as claimed in claim 6, which includes sending said write data of said first write request through said writeback queue to said main memory.
Claim 13
Dependent Claim
54 words
The method as claimed in claim 11, which includes retrieving a block of data from said main memory, merging said write data of said first write request with said block of data retrieved from main memory to form a block of merged data, and loading the block of merged data into said writeback queue.
Claim 14
Independent Claim
305 words
A method of operating a digital computer system having a processor and a cache memory, and a main memory, said method comprising the steps of: storing ownership information in association with blocks of data in said cache memory, said ownership information indicating whether said cache memory owns each block of data stored in said cache memory; sending writeback transactions from said processor and cache memory through a writeback queue to said main memory, and sending non-writeback transactions from said processor and cache memory through a non-writeback queue to said main memory; and accessing data in said cache memory, and upon finding error in the data accessed in said cache memory, entering an error transition mode to provide limited use of data in said cache; wherein said method during said error transition mode includes a) when said processor makes a memory access request for data not owned in said cache memory, making a memory access to said main memory instead of said cache memory, even when said memory access request is for data in a block of data in said cache memory; b) when said processor makes a memory read request for data owned by said cache memory, making a read access to said cache memory; and c) when said processor makes a first memory write request to a block of data not owned in said cache memory followed by a second memory write request to a block of data owned in said cache memory, (i) sending the write data of said first memory write request through said non-writeback queue to said main memory, and then (ii) sending the write data of said second memory write request through said non-writeback queue to said main memory, and sending a writeback of said block of data owned in said cache through said writeback queue to said main memory.
Claim 15
Independent Claim
305 words
A method of operating a digital computer system having a processor and a cache memory, and a main memory, said method comprising the steps of: storing ownership information in association with blocks of data in said cache memory, said ownership information indicating whether said cache memory owns each block of data stored in said cache memory; sending writeback transactions from said processor and cache memory through a writeback queue to said main memory, and sending non-writeback transactions from said processor and cache memory through a non-writeback queue to said main memory; and accessing data in said cache memory, and upon finding error in the data accessed in said cache memory, entering an error transition mode to provide limited use of data in said cache; wherein said method during said error transition mode includes a) when said processor makes a memory access request for data not owned in said cache memory, making a memory access to said main memory instead of said cache memory, even when said memory access request is for data in a block of data in said cache memory; b) when said processor makes a memory read request for data owned by said cache memory, making a read access to said cache memory; and c) when said processor makes a first memory write request to a block of data not owned in said cache memory followed by a second memory write request to a block of data owned in said cache memory, (i) sending the write data of said first memory write request through said non-writeback queue to said main memory, and then (ii) sending the write data of said second memory write request through said non-writeback queue to said main memory, and sending a writeback of said block of data owned in said cache through said writeback queue to said main memory.
Claim 16
Dependent Claim
64 words
The method as claimed in claim 13, wherein said main memory receives said write data of said second memory write request before said writeback of said block of data owned by said cache memory, and waits for receipt of said writeback of said block of data owned in said cache memory before writing to memory said write data of said second memory write request.
Claim 17
Dependent Claim
37 words
The method as claimed in claim 13, which includes changing said ownership information in said cache memory to indicate that said block of data owned by said cache memory is no longer owned by said cache memory.
Claim 18
Dependent Claim
40 words
The method as claimed in claim 13, wherein said writeback of said block of data owned in said cache is loaded into said writeback queue after said write data of said second memory request is loaded into said non-writeback queue.
Claim 19
Dependent Claim
27 words
The method as claimed in claim 13, wherein removal of writebacks from said writeback queue is given priority over removal of write data from said non-writeback queue.
Claim 20
Dependent Claim
288 words
A digital computer system comprising: a processor having a cache memory, said cache memory containing ownership information in association with blocks of data in said cache memory, said ownership information indicating whether said cache memory owns each block of data contained in said cache memory; a main memory; a writeback queue interconnecting said processor and cache memory to said main memory for queuing writeback transactions from said cache memory to said main memory; a non-writeback queue interconnecting said processor and cache memory to said main memory for queuing non-writeback transactions from said processor and cache memory to said main memory; and control means coupled to said processor and cache memory, said writeback queue, and said non-writeback queue, for controlling limited use of data in said cache upon detecting erroneous data in said cache, said control means including a) means, responsive to a memory access request for data not owned in said cache memory, for making a memory access to said main memory instead of said cache memory, even when said memory access request is for data in a block of data in said cache memory; b) means, responsive to a memory read request for data owned by said cache memory, for making a read access to said cache memory; and c) means, responsive to a first memory write request to a block of data not owned in said cache memory followed by a second memory write request to a block of data owned in said cache memory, for preventing write data of said first memory write request from being received by said main memory after write data of said second memory write request while permitting writeback of data from said block of data owned in said cache memory.
Claim 21
Dependent Claim
288 words
A digital computer system comprising: a processor having a cache memory, said cache memory containing ownership information in association with blocks of data in said cache memory, said ownership information indicating whether said cache memory owns each block of data contained in said cache memory; a main memory; a writeback queue interconnecting said processor and cache memory to said main memory for queuing writeback transactions from said cache memory to said main memory; a non-writeback queue interconnecting said processor and cache memory to said main memory for queuing non-writeback transactions from said processor and cache memory to said main memory; and control means coupled to said processor and cache memory, said writeback queue, and said non-writeback queue, for controlling limited use of data in said cache upon detecting erroneous data in said cache, said control means including a) means, responsive to a memory access request for data not owned in said cache memory, for making a memory access to said main memory instead of said cache memory, even when said memory access request is for data in a block of data in said cache memory; b) means, responsive to a memory read request for data owned by said cache memory, for making a read access to said cache memory; and c) means, responsive to a first memory write request to a block of data not owned in said cache memory followed by a second memory write request to a block of data owned in said cache memory, for preventing write data of said first memory write request from being received by said main memory after write data of said second memory write request while permitting writeback of data from said block of data owned in said cache memory.
Claim 22
Dependent Claim
87 words
The digital computer system as claimed in claim 18, wherein said means for preventing includes means for sending the write data of write requests through said non-writeback queue to said main memory, regardless of whether the write data of the write requests are included in blocks of data owned in said cache memory, and means for disowning and writing back through said writeback queue blocks of data owned in said cache that are accessed by the write requests sent through said non-writeback queue to said main memory.
Claim 23
Dependent Claim
59 words
The computer system as claimed in claim 18, wherein said means for preventing includes write order conflict detection means responsive to write order conflict between writebacks in said writeback queue and memory write requests in said non-writeback queue for selecting priority of removal of memory write requests from said non-writeback queue over removal of writebacks from said writeback queue.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |