Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing

Claim 2

A non-interruptive, pipelined cache memory for use in a data processing system including a central processing unit and a main memory connected to said central processing unit via a system bus, which comprises: an address converter connected to said address bus for converting a logical address into a physical address; at least one address array for storing a physical address from said main memory; at least one data array for storing data from said main memory corresponding to said physical address stored in said address array; an address register for storing a physical address from said address converter; a data array address register for storing a data address of data stored in said data array; at least one comparator for comparing a physical address from said address converter with a physical address from said address array to produce either a cache hit signal which causes said data in said data array to be read out on said system bus or a cache miss signal which causes a block of data to be loaded in said data array from said main memory; an error detector for detecting generation of an error in data from said data array and generating an error signal at detection; address back-up register means connected to said address register for storing a physical address of said data from said data array in response to said error signal; data array address back-up register means connected to said data array address register for storing a data address of said data from said data array in response to said error signal; and a system control unit which comprises means for enabling the transfer of said physical address from said address register to said address back-up register means and said data address from said data array register to said data array address back-up register means and means for enabling a physical address of a next request to be stored in said address register now empty and a data address of said next request to be stored in said data array address register so that data is read out of said main memory without interrupting a pipeline operation of said cache memory.

Claim 3

The cache memory of claim 1, which further comprises control, error recovery cycle and pseudo acknowledge registers arranged such that said data is read out of said main memory in response to said error signal.

Claim 4

The cache memory of claim 1, wherein said address back-up register means comprises an address back-up register connected in parallel with said address register.

Claim 5

The cache memory of claim 1, wherein said data array address back-up register means comprises a data array address back-up register connected in parallel with said data address register.

Claim 6

The cache memory of claim 3, wherein said address back-up register means comprises: a memory address register connected to said main memory via a memory bus; and three-state buffer means connected at its input to both said address register and said address back-up register and at its output to said memory address register so as to selectively set said physical address of said address back-up register in said memory address in response to said error signal so that said main memory is accessed according to said physical address in said memory address register in response to said error signal.

Claim 7

The cache memory of claim 4, wherein said data array address back-up register means comprises three-state buffer means connected at its input to both said data array address register and said data array address back-up register and at its output to said address array so as to selectively write an output of said data array address back-up register in said address array in response to said error signal.

Claim 8

A non-interruptive, pipelined cache memory for use in a data processing system which includes a central processing unit and a main memory connected to said central processing unit via a system bus, which comprises: an address converter connected to said address bus for converting a logical address into a physical address; at least one address array for storing a physical address from said main memory; at least one data array for storing data from said main memory corresponding to said physical address stored in said address array; an address register for storing a physical address from said address converter; a data array address register for storing a data address of data stored in said data array; at least one comparator for comparing a physical address from said address converter with a physical address from said address array to produce either a cache hit signal which causes said data in said data array to be read out on said system bus or a cache miss signal which causes a block of data to be loaded in said data array from said main memory; an error detector for detecting generation of an error in data from said data array and generating an error signal at detection; address back-up register means connected to said address register for storing a physical address of said data from said data array in response to said error signal; data array address back-up register means connected to said data array address register for storing a data address of said data from said data array in response to said error signal; request code back-up register means connected to said system bus for storing REQ and CODE signals in response to said error signal; and a system control unit which comprises means for enabling the transfer of said physical address from said address register to said address back-up register means and said data address from said data array register to said data array address back-up register means and means for enabling a physical address of a next request to be stored in said address register now empty and a data address of said next request to be stored in said data array address register so that data is read out of said main memory without interrupting a pipeline operation of said cache memory.

Claim 9

A non-interruptive, pipelined cache memory for use in a data processing system which includes a central processing unit and a main memory connected to said central processing unit via a system bus, which comprises: an address converter connected to said address bus for converting a logical address into a physical address; at least one address array for storing a physical address from said main memory; at least one data array for storing data from said main memory corresponding to said physical address stored in said address array; an address register for storing a physical address from said address converter; a data array address register for storing a data address of data stored in said data array; at least one comparator for comparing a physical address from said address converter with a physical address from said address array to produce either a cache hit signal which causes said data in said data array to be read out on said system bus or a cache miss signal which causes a block of data to be loaded in said data array from said main memory; an error detector for detecting generation of an error in data from said data array and generating an error signal at detection; address back-up register means connected to said address register for storing a physical address of said data from said data array in response to said error signal; data array address back-up register means connected to said data array address register for storing a data address of said data from said data array in response to said error signal; request code back-up register means connected to said system bus for storing REQ and CODE signals in response to said error signal; and a system control unit which comprises means for enabling the transfer of said physical address from said address register to said address back-up register means and said data address from said data array register to said data array address back-up register means and means for enabling a physical address of a next request to be stored in said address register now empty and a data address of said next request to be stored in said data array address register so that data is read out of said main memory without interrupting a pipeline operation of said cache memory.