Protection structure against latch-up in a CMOS circuit

Claim 2

A CMOS circuit protected against latch-up, comprising: internal circuitry connected between a first more positive supply terminal and a second more negative supply terminal to draw power therefrom, said internal circuitry having, as known parameters, a current I 1 and a voltage V 1 for the triggering of the latch-up phenomenon; a limiter, connected, in parallel with the internal circuitry, between the first supply terminal and the second supply terminal, this limiter having a triggering threshold below voltage V 1 and consuming current of a value far higher than I 1 when a voltage of V 1 or greater is applied between the first and second supply terminals.

Claim 3

A CMOS circuit according to claim 1, wherein the triggering threshold of said limiter is higher than a maximum voltage permitted for the operation of the CMOS internal circuitry.

Claim 4

A CMOS circuit according to claim 1, wherein said limiter comprises zener diodes that are operatively connected in series between the first supply terminal and the second supply terminal, the sum of the reverse-breakdown threshold voltages of the diodes being equal to the triggering threshold of said limiter.

Claim 5

A CMOS circuit according to claim 1, wherein said limiter comprises two zener diodes in series, each diode having a threshold of the order of 6 volts.

Claim 6

A CMOS circuit according to claim 1, further comprising a protection circuit against electrostatic discharges which is connected, in parallel with said limiter, between said first supply terminal and said second supply terminal.

Claim 7

A CMOS circuit according to claim 1, further comprising a protection resistor which is placed in series between said first supply terminal and said limiter.

Claim 8

A CMOS circuit according to claim 1, further comprising: a protection resistor which is placed in series between said first supply terminal and said limiter; and a lateral bipolar transistor, having a collector connected to said first supply terminal, and an emitter and a base connected to said second supply terminal.

Claim 9

A CMOS circuit according to claim 1, wherein said limiter is a lateral bipolar transistor, one collector of which is connected to said first supply terminal, and one emitter and one base of which is connected to said second supply terminal, and wherein said base has been overdoped to diminish a collector-base avalanche voltage.

Claim 10

The integrated circuit of claim 1, wherein said limiter has a threshold voltage in the range of about 10-15 V inclusive.

Claim 11

The integrated circuit of claim 1, wherein said power supply connections are specified for connection for approximately 5 Volts of supply voltage, and said limiter has a threshold voltage of about 12 V.

Claim 12

The integrated circuit of claim 1, wherein said limiter has a dynamic on-resistance of no more than a few tens of ohms.

Claim 13

The integrated circuit of claim 1, wherein said limiter comprises multiple Zener diodes in series.

Claim 14

A CMOS integrated circuit, comprising: first and second power supply input connections; a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax; a limiter circuit, having a nonlinear response with a low dynamic impedance R e at applied voltages greater than a threshold voltage E; said limiter being connected, in series with a resistance, between said first and second power supply connections; an electrostatic discharge protection device, connected directly between said first and second power supply connections, said electrostatic discharge protection device having a nonlinear response with a very low impedance at applied voltages greater than a threshold voltage Vo; wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E<Vo.

Claim 15

A CMOS integrated circuit, comprising: first and second power supply input connections; a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax; a limiter circuit, having a nonlinear response with a low dynamic impedance R e at applied voltages greater than a threshold voltage E; said limiter being connected, in series with a resistance, between said first and second power supply connections; an electrostatic discharge protection device, connected directly between said first and second power supply connections, said electrostatic discharge protection device having a nonlinear response with a very low impedance at applied voltages greater than a threshold voltage Vo; wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E<Vo.

Claim 16

The integrated circuit of claim 13, wherein said limiter has a threshold voltage in the range of about 10-15 V inclusive.

Claim 17

The integrated circuit of claim 13, wherein said power supply connections are specified for connection to approximately 5 Volts of supply voltage, and said limiter has a threshold voltage of about 12 V.

Claim 18

The integrated circuit of claim 13, wherein said limiter has a dynamic on-resistance of no more than a few tens of ohms.

Claim 19

The integrated circuit of claim 13, wherein said limiter has a dynamic on-resistance of about 20 ohms.

Claim 20

The integrated circuit of claim 13, wherein said limiter comprises multiple Zener diodes in series.

Claim 21

A CMOS integrated circuit, comprising: first and second power supply input connections; a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax; said plurality of active devices collectively having a latchup trigger voltage of least V1, and a latchup holding current of at least I1; a limiter circuit, comprising a Zener diode structure having a threshold voltage E; said limiter being connected, in series with a resistance, between said first and second power supply connections; an electrostatic discharge protection device, comprising a diode-connected bipolar transistor connected directly between said first and second power supply connections, said electrostatic discharge protection device having a threshold voltage Vo; wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E, E<V1, and E<Vo.

Claim 22

A CMOS integrated circuit, comprising: first and second power supply input connections; a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax; said plurality of active devices collectively having a latchup trigger voltage of least V1, and a latchup holding current of at least I1; a limiter circuit, comprising a Zener diode structure having a threshold voltage E; said limiter being connected, in series with a resistance, between said first and second power supply connections; an electrostatic discharge protection device, comprising a diode-connected bipolar transistor connected directly between said first and second power supply connections, said electrostatic discharge protection device having a threshold voltage Vo; wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E, E<V1, and E<Vo.

Claim 23

The integrated circuit of claim 19, wherein said limiter has a threshold voltage in the range of about 10-15 V inclusive.

Claim 24

The integrated circuit of claim 19, wherein said power supply connections are specified for connection to approximately 5 Volts of supply voltage, and said limiter has a threshold voltage of about 12 V.

Claim 25

The integrated circuit of claim 19, wherein said limiter has a dynamic on-resistance of no more than a few tens of ohms.

Claim 26

The integrated circuit of claim 19, wherein said limiter has a dynamic on-resistance of about 20 ohms.

Claim 27

The integrated circuit of claim 19, wherein said limiter comprises multiple Zener diodes in series.