EP0324185A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Input protecting circuit in use with a MOS semiconductor device
Assignee: Toshiba Corp
•
Filing: 1988-12-30
•
Granted: —
•
Expires: 2008-12-30
Abstract
Abstract A bipolar transistor (14) for clamping an excess input potential is provided near an input pad (11). A signal from the input pad (11) is supplied through a wire (12) to the gate of a MOS transistor (13) in the input stage. A diode (15) is provided near the gate of the MOS transistor (13). The diode absorbs a potential oscillation generated in the wire (12) near the gate of the transistor (13), which is due to action of an inductance (L) involved in the wire (12).
Inventors
- 👤 Shigeru C/O Patent Division Atsumi
- 👤 Toru C/O Patent Division Yoshida
- 👤 Yasuo C/O Patent Division Kawahara
- 👤 Fuminari C/O Patent Division Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 01:02
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/611; H10D89/711; H10D89/931
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
110 words
An input protecting circuit in use with a MOS semiconductor device comprising: an input pad (11); a MOS transistor (13, 50, 56) in the input stage of the MOS semiconductor device, the gate of which receives a signal from said input pad; a wire (12, 41, 25, 45, 46) interconnecting said input pad and the gate of said MOS transistor in said input stage; a first protecting element (14, 16, 17, 18) provided near said input pad and connected at one end to said interconnecting wire; and a second protecting element (15, 19) provided near the gate of said MOS transistor and connected at one end to said interconnecting wire.
Claim 2
Dependent Claim
110 words
An input protecting circuit in use with a MOS semiconductor device comprising: an input pad (11); a MOS transistor (13, 50, 56) in the input stage of the MOS semiconductor device, the gate of which receives a signal from said input pad; a wire (12, 41, 25, 45, 46) interconnecting said input pad and the gate of said MOS transistor in said input stage; a first protecting element (14, 16, 17, 18) provided near said input pad and connected at one end to said interconnecting wire; and a second protecting element (15, 19) provided near the gate of said MOS transistor and connected at one end to said interconnecting wire.
Claim 3
Dependent Claim
41 words
An input protecting circuit according to claim 1, characterized in that said second protecting element is formed in a circuit block (54) which is enclosed by a guard ring region and contains said MOS transistor of the input stage formed therein.
Claim 4
Dependent Claim
20 words
An input protecting circuit according to claim 1, characterized in that said first protecting element is one bipolar transistor (14).
Claim 5
Dependent Claim
22 words
An input protecting circuit according to claim 1, characterized in that said first protecting element includes a pair of diodes (16, 17).
Claim 6
Dependent Claim
23 words
An input protecting circuit according to claim 1, characterized in that said first protecting element includes a pair of bipolar transistors (14, 18).
Claim 7
Dependent Claim
19 words
An input protecting circuit according to claim 1, characterized in that said second protecting element includes a diode (15).
Claim 8
Dependent Claim
32 words
An input protecting circuit according to claim 1, characterized in that said second protecting element includes a MOS transistor (19) of which the source and drain are connected to said wire (12).
Claim 9
Dependent Claim
20 words
An input protecting circuit according to claim 7, characterized in that the gate of said MOS transistor (19) is grounded.
Claim 10
Dependent Claim
25 words
An input protecting circuit according to claim 7, characterized in that the gate of said MOS transistor (19) is connected to a power source potential.
Claim 11
Dependent Claim
21 words
An input protecting circuit according to claim 1, characterized in that a resistor (R) is inserted in series in said wire.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.