Circuit for preventing latch-up of parasitic thyristor formed in CMOS integrated circuit

Claim 2

A CMOS circuit comprising in combination: at least one P channel field effect transistor and at least one N channel field effect transistor, both formed on a predetermined region of a semiconductor substrate; first and second power supply connections for supplying operating power to the CMOS circuit, the P channel and N channel field effect transistors being so arranged on the semiconductor substrate as to produce a parasitic thyristor between said power supply connections, said parasitic thyristor having a holding current level above which said thyristor is maintained in the latched-up condition after being turned on and below which said thyristor is off, and protection means for preventing the latch-up of said parasitic thyristor in said CMOS circuit, said protection means comprising variable resistance conductor means interposed in series with said power supply connections for passing current to the CMOS circuit and having a critical current level above which the variable resistance conductor means exhibits a sharply increased resistance, the variable resistance conductor means being so constructed and arranged as to establish the critical current level above the current level normally drawn by the CMOS circuit but below said holding current level thereby to provide power for operation of said CMOS circuit but to prevent latch-up of the parasitic thyristor, the sharply increased resistance characteristic of the variable resistance conductor means responding with sufficient speed to the triggering of the parasitic thyristor as to reach said sharply increased resistance to prevent parasitic thyristor latch-up.

Claim 3

The combination as set forth in claim 1 wherein the variable resistance conductor means comprises a superconductor having a critical current density, and means for limiting the critical current density to said critical current level over at least a portion of said superconductor.

Claim 4

The combination as set forth in claim 2 wherein the means for limiting comprises a reduced cross-sectional area formed in said superconductor.

Claim 5

The combination as set forth in claim 2 wherein said superconductor comprises a composite superconductor including two superconductor materials having different critical current densities, one of said superconducting materials so constructed and arranged as to establish said critical current level.

Claim 6

The combination as set forth in claim 2 wherein the means for limiting comprises means for applying a magnetic field to at least a part of said superconductor, the magnetic field being related to the current flowing to the CMOS circuit from the power supply.

Claim 7

A CMOS system comprising: a power supply; a plurality of CMOS circuits arranged to be commonly powered from the power supply, each CMOS circuit including at least one P channel field effect transistor and at least one N channel field effect transistor, both formed on a predetermined region of a semiconductor substrate, first and second power supply connections for supplying operating power to the CMOS circuit, the P channel and N channel field effect transistor being so arranged on the semiconductor substrate as to produce a parasitic thyristor between said power supply connections, said parasitic thyristor having a holding current level above which said thyristor is maintained in the latch-up position after being turned on and below which said thyristor is off; and a plurality of protection means for preventing the latch-up of said parasitic thyristors in said CMOS circuits, said plurality of protection means including a plurality of variable resistance conductor means coupled between the power supply and respective ones of the CMOS circuits, each variable resistance conductor means being interposed in series with said power supply connections for passing current to the CMOS circuit and having a critical current level above which the variable resistance conductor means exhibits a sharply increased resistance, the variable resistance conductor means being so constructed and arranged as to establish the critical current level above the current level normally drawn by the CMOS circuit but below said holding current level thereby to provide power for operation of said CMOS circuit but the prevent latch-up of the parasitic thyristor, the sharply increased resistance characteristic of the variable resistance conductor means responding with sufficient speed to the triggering of the parasitic thyristor as to reach said sharply increased resistance to prevent parasitic thyristor latch-up.

Claim 8

A CMOS system comprising: a power supply; a plurality of CMOS circuits arranged to be commonly powered from the power supply, each CMOS circuit including at least one P channel field effect transistor and at least one N channel field effect transistor, both formed on a predetermined region of a semiconductor substrate, first and second power supply connections for supplying operating power to the CMOS circuit, the P channel and N channel field effect transistor being so arranged on the semiconductor substrate as to produce a parasitic thyristor between said power supply connections, said parasitic thyristor having a holding current level above which said thyristor is maintained in the latch-up position after being turned on and below which said thyristor is off; and a plurality of protection means for preventing the latch-up of said parasitic thyristors in said CMOS circuits, said plurality of protection means including a plurality of variable resistance conductor means coupled between the power supply and respective ones of the CMOS circuits, each variable resistance conductor means being interposed in series with said power supply connections for passing current to the CMOS circuit and having a critical current level above which the variable resistance conductor means exhibits a sharply increased resistance, the variable resistance conductor means being so constructed and arranged as to establish the critical current level above the current level normally drawn by the CMOS circuit but below said holding current level thereby to provide power for operation of said CMOS circuit but the prevent latch-up of the parasitic thyristor, the sharply increased resistance characteristic of the variable resistance conductor means responding with sufficient speed to the triggering of the parasitic thyristor as to reach said sharply increased resistance to prevent parasitic thyristor latch-up.

Claim 9

A CMOS circuit comprising at least a single P channel field effect transistor, at least a single N channel field effect transistor, both of said field effect transistors formed on a predetermined region of a semiconductor substrate, first and second power supply connections for providing power to the CMOS circuit, a parasitic thyristor formed over a semiconductor region of said P channel transistor and a semiconductor region of said N channel transistor and being formed between said first and second power supply connections, said CMOS circuit being in a latched-up conduction when the current flow through said parasitic thyristor is greater than a latch-up holding current, and means for protecting said CMOS circuit from latch-up, said protecting means comprising: variable resistance conductor means connected to at least one of said first and second power supply connections, the resistance value of said variable resistance conductor means being sharply increased when current greater than said latch-up holding current flows through said at least one of said first and second power supply connections, the sharply increased resistance characteristic of the variable resistance conductor means responding with sufficient speed to the triggering of the parasitic thyristor as to reach said sharply increased resistance to prevent latch-up of the parasitic thyristor.

Claim 10

A CMOS circuit comprising at least a single P channel field effect transistor, at least a single N channel field effect transistor, both of said field effect transistors formed on a predetermined region of a semiconductor substrate, first and second power supply connections for providing power to the CMOS circuit, a parasitic thyristor formed over a semiconductor region of said P channel transistor and a semiconductor region of said N channel transistor and being formed between said first and second power supply connections, said CMOS circuit being in a latched-up conduction when the current flow through said parasitic thyristor is greater than a latch-up holding current, and means for protecting said CMOS circuit from latch-up, said protecting means comprising: variable resistance conductor means connected to at least one of said first and second power supply connections, the resistance value of said variable resistance conductor means being sharply increased when current greater than said latch-up holding current flows through said at least one of said first and second power supply connections, the sharply increased resistance characteristic of the variable resistance conductor means responding with sufficient speed to the triggering of the parasitic thyristor as to reach said sharply increased resistance to prevent latch-up of the parasitic thyristor.

Claim 11

A latch-up protective circuit in accordance with claim 7, wherein said variable resistance conductor means comprises a superconductor having a critical current level which is less than the value of said latch-up holding current.

Claim 12

A latch-up protective circuit in accordance with claim 8, wherein said superconductor material has a region having a reduced cross-sectional area in at least a part thereof, said reduced cross-sectional level being diminished to establish the critical current level at a level less than said latch-up holding current.

Claim 13

A latch-up protective circuit in accordance with claim 9, wherein the value of said reduced cross-sectional area is set such the level of current flowing through the variable resistance conductor means is less than the value of said latch-up holding current, both when the superconductor is in its superconducting state and in its normal conducting state.

Claim 14

A latch-up protective circuit in accordance with claim 8, wherein said superconductor is formed by connecting in series a plurality of types of superconductor materials having different critical current values.

Claim 15

A latch-up protective circuit in accordance with claim 8, which further comprises normal conductor material means for carrying current to said CMOS circuit and disposed in contact with at least a part of said superconductor.

Claim 16

A latch-up protective circuit in accordance with claim 8, which further comprises magnetic field applying means provided closely adjacent to at least a part of said superconductor for generating a magnetic field in response to current flow to said CMOS circuit, and applying said magnetic field to said superconductor.