Patent US5347145A successfully refreshed from Google Patents.
US5347145A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pad arrangement for a semiconductor device
Assignee: Toshiba Corp
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Filing: 1991-12-26
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Granted: 1994-09-13
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Expires: 2011-12-26
Abstract
Abstract A semiconductor device comprises a rectangular semiconductor chip provided with an integrated circuit, and a plurality of voltage stress examination pads formed on the semiconductor chip for applying stress examination voltage to the integrated circuit, and having the same function, wherein the voltage stress examination pads are provided on opposite sides of the semiconductor chip.
Inventors
- 👤 Hiroaki Tanaka
- 👤 Masaru Koyanagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:30
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G01R31/30; G01R31/316; G01R31/3161; H10P; H10P74/00; H10P74/27; H10P74/273; H10W72/50; H10W72/541; H10W72/5449; H10W72/931; H10W72/932; H10W72/951
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
101 words
A semiconductor device, comprising: a rectangular semiconductor chip including an integrated circuit; a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination voltage to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said rectangular semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said rectangular semiconductor chip, said second side being opposite said first side.
Claim 2
Dependent Claim
101 words
A semiconductor device, comprising: a rectangular semiconductor chip including an integrated circuit; a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination voltage to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said rectangular semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said rectangular semiconductor chip, said second side being opposite said first side.
Claim 3
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the first and second pads of each group are aligned with each other.
Claim 4
Dependent Claim
22 words
The semiconductor device according to claim 1, wherein the first and second pads of each group are offset relative to each other.
Claim 5
Dependent Claim
34 words
The semiconductor device according to claim 1, wherein a pad of a first group arranged adjacent to said first side is aligned with a pad of a second group adjacent to said second side.
Claim 6
Dependent Claim
74 words
The semiconductor device according to claim 1, wherein each group of pads includes a first pad adjacent to said first side of said rectangular semiconductor chip, a second pad adjacent to said second side of said rectangular semiconductor chip, a third pad adjacent to a third side of said rectangular semiconductor chip, and a fourth pad adjacent to a fourth side of said rectangular semiconductor chip, said fourth side being opposite said third side.
Claim 7
Dependent Claim
20 words
The semiconductor device according to claim 1, wherein the pads of each group are connected to each other by wire.
Claim 8
Dependent Claim
19 words
The semiconductor device according to claim 1, wherein said voltage stress examination pads are made of a conductive rubber.
Claim 9
Dependent Claim
29 words
The semiconductor device according to any one of claims 1, 2, 3 or 4, wherein said semiconductor chip is one of a plurality of chips on a semiconductor wafer.
Claim 10
Dependent Claim
29 words
The semiconductor device according to any one of claims 1, 2 or 6, wherein the semiconductor chip is accommodated in a package, and is finished as an IC device.
Claim 11
Dependent Claim
101 words
A semiconductor device, comprising: a rectangular semiconductor chip having an integrated circuit; a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination signal to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said rectangular semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said rectangular semiconductor chip, said second side being opposite said first side.
Claim 12
Dependent Claim
101 words
A semiconductor device, comprising: a rectangular semiconductor chip having an integrated circuit; a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination signal to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said rectangular semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said rectangular semiconductor chip, said second side being opposite said first side.
Claim 13
Dependent Claim
21 words
The semiconductor device according to claim 10, wherein the first and second pads of each group are aligned with each other.
Claim 14
Dependent Claim
22 words
The semiconductor device according to claim 10, wherein the first and second pads of each group are offset relative to each other.
Claim 15
Dependent Claim
32 words
The semiconductor device according to claim 10, wherein a pad of a first group arranged on said first side is aligned with a pad of a second group on said second side.
Claim 16
Dependent Claim
74 words
The semiconductor device according to claim 10, wherein each group of pads includes a first pad adjacent to said first side of said rectangular semiconductor chip, a second pad adjacent to said second side of said rectangular semiconductor chip, a third pad adjacent to a third side of said rectangular semiconductor chip, and a fourth pad adjacent to a fourth side of said rectangular semiconductor chip, said fourth side being opposite said third side.
Claim 17
Dependent Claim
20 words
The semiconductor device according to claim 10, wherein the pads of each group are connected to each other by wire.
Claim 18
Dependent Claim
19 words
The semiconductor device according to claim 10, wherein said voltage stress examination pads are made of a conductive rubber.
Claim 19
Dependent Claim
27 words
The semiconductor device according to any one of claims 10 to 14, wherein said semiconductor chip is one of a plurality of chips on a semiconductor wafer.
Claim 20
Dependent Claim
28 words
The semiconductor device according to any one of claims 10 to 14, wherein the semiconductor chip is accommodated in a package, and is finished as an IC device.
Claim 21
Dependent Claim
98 words
A semiconductor device, comprising: semiconductor chips arranged in rows and columns on a semiconductor wafer, each semiconductor chip including an integrated circuit; a plurality of pads on each semiconductor chip connected to the corresponding integrated circuit, each semiconductor chip including a group of pads, wherein the pads of each group are connected to each other, a first pad of said group is arranged adjacent to a first side of said semiconductor chip, and a second pad of said group is arranged adjacent to a second side of said semiconductor chip, said second side being opposite said first side.
Claim 22
Dependent Claim
98 words
A semiconductor device, comprising: semiconductor chips arranged in rows and columns on a semiconductor wafer, each semiconductor chip including an integrated circuit; a plurality of pads on each semiconductor chip connected to the corresponding integrated circuit, each semiconductor chip including a group of pads, wherein the pads of each group are connected to each other, a first pad of said group is arranged adjacent to a first side of said semiconductor chip, and a second pad of said group is arranged adjacent to a second side of said semiconductor chip, said second side being opposite said first side.
Claim 23
Dependent Claim
29 words
The semiconductor device according to claim 19, wherein the first pad of a first group is aligned along the column direction with the second pad of the first group.
Claim 24
Dependent Claim
31 words
The semiconductor device according to claim 19, wherein the first pad of a first group is offset in a column direction with respect to the second pad of the first group.
Claim 25
Dependent Claim
37 words
The semiconductor device according to claim 19, wherein each semiconductor chip includes at least two groups of pads, one pad of a first group being aligned in the column direction with one pad of a second group.
Claim 26
Dependent Claim
90 words
The semiconductor device according to claim 19, wherein at least one semiconductor chip is a rectangular semiconductor chip and includes a group of pads comprising a first pad adjacent to said first side of said one rectangular semiconductor chip, a second pad adjacent to said second side of said one rectangular semiconductor chip, a third pad adjacent to a third side of said one rectangular semiconductor chip, and a fourth pad adjacent to a fourth side of said one rectangular semiconductor chip, said fourth side being opposite said third side.
Claim 27
Dependent Claim
20 words
The semiconductor device according to claim 19, wherein the pads of each group are connected to each other by wire.
Claim 28
Independent Claim
187 words
A system for simultaneously subjecting a plurality of integrated circuits in semiconductor chip regions to a voltage stress examination, said semiconductor chip regions arranged in rows and columns on a semiconductor wafer and each semiconductor chip region having groups of voltage stress examination pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said each semiconductor chip region, and a second pad of each group is arranged on a second side of said each semiconductor chip region, said second side being opposite said first side, wherein said system includes a probe card having probes extending from opposed first and second sides thereof, the probes extending from the first side being arranged to contact, during the voltage stress examination, voltage examination pads adjacent to a side of a first semiconductor region in a first row and voltage examination pads adjacent to a side of a second semiconductor chip region in a second row, wherein said side of said second semiconductor chip region is adjacent to said side of said first semiconductor region.
Claim 29
Independent Claim
187 words
A system for simultaneously subjecting a plurality of integrated circuits in semiconductor chip regions to a voltage stress examination, said semiconductor chip regions arranged in rows and columns on a semiconductor wafer and each semiconductor chip region having groups of voltage stress examination pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said each semiconductor chip region, and a second pad of each group is arranged on a second side of said each semiconductor chip region, said second side being opposite said first side, wherein said system includes a probe card having probes extending from opposed first and second sides thereof, the probes extending from the first side being arranged to contact, during the voltage stress examination, voltage examination pads adjacent to a side of a first semiconductor region in a first row and voltage examination pads adjacent to a side of a second semiconductor chip region in a second row, wherein said side of said second semiconductor chip region is adjacent to said side of said first semiconductor region.
Claim 30
Dependent Claim
162 words
The system according to claim 25, wherein each group of pads includes a first pad adjacent to said first side of said semiconductor chip, a second pad adjacent to said second side of said semiconductor chip, a third pad adjacent to a third side of said semiconductor chip, and a fourth pad adjacent to a fourth side of said semiconductor chip, said fourth side being opposite said third side, and wherein said probe includes third and fourth opposed sides substantially perpendicular to said first and second opposed sides and having probes extending therefrom, the probes extending from the third side being arranged to contact, during the voltage stress examination, voltage examination pads adjacent to a side of a third semiconductor region in a first column and voltage examination pads adjacent to a side of a fourth semiconductor chip region in a second column, wherein said side of said third semiconductor chip region is adjacent to said side of said fourth semiconductor region.
Claim 31
Dependent Claim
90 words
A semiconductor device, comprising: a semiconductor chip including an integrated circuit; a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination signal to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said semiconductor chip.
Claim 32
Dependent Claim
90 words
A semiconductor device, comprising: a semiconductor chip including an integrated circuit; a plurality of voltage stress examination pads on said semiconductor chip for receiving a stress examination signal to be applied to said integrated circuit, said voltage stress examination pads including groups of pads, wherein the pads of each group are connected to each other, a first pad of each group is arranged adjacent to a first side of said semiconductor chip, and a second pad of each group is arranged adjacent to a second side of said semiconductor chip.
References Cited (Backward Citations)
US4413271A
Cited
JPS60240140A
Cited
US4833620A
Cited
DE3712178A1
Cited
US4808844A
Cited
US4934820A
Cited
EP0317963A2
Cited
US5083181A
Cited
US4884122A
Cited
US4974053A
Cited
US5008827A
Cited
US5138427A
Cited
US5073816A
Cited
US5047711A
Cited
US5065227A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |