Patent US3254904A successfully refreshed from Google Patents.
Patent US4447565A successfully refreshed from Google Patents.
Patent US5346843A successfully refreshed from Google Patents.
US5346843A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device having a memory cell and peripheral circuit including forming a first electrode for the capacitor
Assignee: Sony Corp
•
Filing: 1992-04-21
•
Granted: 1994-09-13
•
Expires: 2012-04-21
Abstract
Abstract According to this invention, a conductive film for forming a plate electrode of a capacitor constituting a memory cell is patterned in only a memory cell region at first. After the conductive film in a peripheral circuit region is used as a stopper for wet-etching a low-melting insulating film of the peripheral circuit region, the conductive film is patterned using the same mask as the low-melting insulating film or the low-melting insulating film itself as a mask. For this reason, an SiN film formed by a low pressure CVD method is not used as a stopper, and an additional lithographic step is not required. Therefore, while a memory cell region is planarized and the step of the peripheral circuit region is reduced, data retaining characteristics can be improved without increasing the number of steps.
Inventors
- 👤 Hideaki Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:25
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10B12/31; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
151 words
A method of manufacturing a semiconductor memory having a memory cell region and a peripheral circuit region, and a memory cell being constituted by a transistor and a capacitor, comprising the steps of: forming a conductive film which comprises a first electrode for a plate electrode of said capacitor; forming a first resist on an entire surface of said peripheral circuit and memory cell regions; patterning said conductive film using said first resist as a mask to form said first electrode; forming a first insulating film on said conductive film so as to planarize said conductive film; forming a second resist on the entire surface of said memory cell region; removing said first insulating film from said peripheral circuit region by wet etching using said second resist as a mask; removing said conductive film from said peripheral circuit region using said second resist as a mask; and removing said second resist.
Claim 2
Independent Claim
151 words
A method of manufacturing a semiconductor memory having a memory cell region and a peripheral circuit region, and a memory cell being constituted by a transistor and a capacitor, comprising the steps of: forming a conductive film which comprises a first electrode for a plate electrode of said capacitor; forming a first resist on an entire surface of said peripheral circuit and memory cell regions; patterning said conductive film using said first resist as a mask to form said first electrode; forming a first insulating film on said conductive film so as to planarize said conductive film; forming a second resist on the entire surface of said memory cell region; removing said first insulating film from said peripheral circuit region by wet etching using said second resist as a mask; removing said conductive film from said peripheral circuit region using said second resist as a mask; and removing said second resist.
Claim 3
Independent Claim
152 words
A method of manufacturing a semiconductor memory having a memory cell region and a peripheral circuit region, and a memory cell being constituted by a transistor and a capacitor, comprising the steps of: forming a conductive film which comprises a first electrode for a plate electrode of said capacitor; forming a first resist on the surface of said peripheral circuit and memory cell regions; patterning said conductive film using said first resist as a mask to form said first electrode; forming a first insulating film on said conductive film so as to planarize said conductive film; forming a second resist on the surface of at least said memory cell region; removing said first insulating film from said peripheral circuit region by wet etching using said second resist as a mask; removing said second resist; and removing said conductive film from said peripheral circuit region using said first insulating film as a mask.
Claim 4
Independent Claim
152 words
A method of manufacturing a semiconductor memory having a memory cell region and a peripheral circuit region, and a memory cell being constituted by a transistor and a capacitor, comprising the steps of: forming a conductive film which comprises a first electrode for a plate electrode of said capacitor; forming a first resist on the surface of said peripheral circuit and memory cell regions; patterning said conductive film using said first resist as a mask to form said first electrode; forming a first insulating film on said conductive film so as to planarize said conductive film; forming a second resist on the surface of at least said memory cell region; removing said first insulating film from said peripheral circuit region by wet etching using said second resist as a mask; removing said second resist; and removing said conductive film from said peripheral circuit region using said first insulating film as a mask.
Claim 5
Dependent Claim
27 words
A method according to claim 1 or claim 2 wherein during the step of removing said first insulating film said conductive film is used as a stopper.
Claim 6
Dependent Claim
15 words
A method according to claim 1 including depositing a BPSG film on said first electrode.
Claim 7
Dependent Claim
15 words
A method according to claim 2 including depositing a BPSG film on said first electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |