Patent US5345234A successfully refreshed from Google Patents.
US5345234A
Expired / Lapsed
US
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Method and apparatus for combining a flash analog to digital converter with digital to analog functions
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-08-31
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Granted: 1994-09-06
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Expires: 2013-08-31
Abstract
Abstract A converter circuit provides analog to digital and digital to analog functions on a single silicon device. A flash analog to digital converter produces digital outputs using comparators which each receive an input signal and which each have different reference voltages. A decoder receiving digital inputs activates switches to connect selected ones of the same voltage references used by the flash analog to digital converter to a buffer which produces an analog output. The converter circuit can be a single or multi-stage flash analog to digital converter operating in a single channel or multi-channel environment. Timing and control logic prevents switching from occurring at times when perturbations on the voltage references could affect the analog and digital outputs.
Inventors
- 👤 Brett Stewart
- 👤 Miki Moyal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:59
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/1205; H03M1/121; H03M1/1215; H03M1/02; H03M1/14; H03M1/145; H03M1/34; H03M1/36; H03M1/361; H03M1/362; H03M1/365; H03M1/66; H03M1/74; H03M1/76; H03M1/765
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
127 words
A converter circuit comprising: a plurality of comparators; an analog input channel for receiving an analog signal and routing said analog signal to first inputs of said comparators; a voltage divider network providing a plurality of different voltage references to second inputs of said comparators, outputs of said comparators thereby forming a digital representation of an amplitude of said analog signal; a plurality of switches, each of said switches being connected between one of said second inputs of said comparators and an analog output, said analog output providing an analog representation of digital inputs; a switch controller controlling each of said switches to connect said one of said second inputs of said comparators to said analog output in response to a logic condition of said digital inputs.
Claim 2
Dependent Claim
127 words
A converter circuit comprising: a plurality of comparators; an analog input channel for receiving an analog signal and routing said analog signal to first inputs of said comparators; a voltage divider network providing a plurality of different voltage references to second inputs of said comparators, outputs of said comparators thereby forming a digital representation of an amplitude of said analog signal; a plurality of switches, each of said switches being connected between one of said second inputs of said comparators and an analog output, said analog output providing an analog representation of digital inputs; a switch controller controlling each of said switches to connect said one of said second inputs of said comparators to said analog output in response to a logic condition of said digital inputs.
Claim 3
Dependent Claim
51 words
The apparatus recited in claim 1, wherein each of said switches comprises a first terminal connected to said analog output, a second terminal connected to a said second terminal of a said comparator, and a control input controlling connection of said first and second terminals of said switch to each other.
Claim 4
Dependent Claim
19 words
The apparatus recited in claim 2, further comprising a buffer circuit between said analog output and an output terminal.
Claim 5
Dependent Claim
35 words
The apparatus recited in claim 1, wherein said voltage divider comprises a resistor ladder having a first resistor connected to a voltage reference and at least one resistor connected in series with said first resistor.
Claim 6
Dependent Claim
21 words
The apparatus recited in claim 1, further comprising a timing control system, said timing control system controlling switching of said switches.
Claim 7
Dependent Claim
45 words
The apparatus recited in claim 5, wherein said timing control system comprises means for controlling said switches to change state during time periods when disturbances to voltage references on said second inputs of said comparators have essentially no effect on said analog and digital outputs.
Claim 8
Dependent Claim
18 words
The apparatus recited in claim 5, comprising a digital decoder connected between said digital inputs and said comparators.
Claim 9
Dependent Claim
20 words
The apparatus recited in claim 5, comprising an encoder connected between said outputs of said comparators and digital output terminals.
Claim 10
Dependent Claim
17 words
The apparatus recited in claim 5, wherein said converter circuit comprises a flash analog and digital converter.
Claim 11
Dependent Claim
18 words
The apparatus recited in claim 9, wherein said converter circuit is a multi-stage flash analog to digital converter.
Claim 12
Dependent Claim
52 words
The apparatus recited in claim 10, wherein said timing control system further comprises means for controlling said switches to change state during time periods when said voltage references on said second inputs of said comparators as a result of switching between stages have essentially no effect on said analog and digital outputs.
Claim 13
Dependent Claim
20 words
The apparatus recited in claim 9, wherein said converter circuit comprises a multiple input channel flash analog to digital converter.
Claim 14
Dependent Claim
77 words
The apparatus recited in claim 12, wherein said plurality of switches comprises: a first plurality of switches, each of said first plurality of switches being connected between said one of said second inputs of said comparators and a first channel analog output; and at least one additional plurality of switches, each of said additional plurality of switches being connected between said one of said second inputs of said comparators and an analog output for an additional channel.
Claim 15
Dependent Claim
43 words
The apparatus recited in claim 13, wherein said timing system comprises a multiplexer for steering decoded said digital inputs to one of said first and additional plurality of switches, such that a desired one of said multiple channels is converted by said converter.
Claim 16
Dependent Claim
15 words
The apparatus recited in claim 14, comprising a channel selector for selecting said desired channel.
Claim 17
Dependent Claim
21 words
The apparatus recited in claim 14, comprising a polling circuit for selecting a sequence of said channels in a predetermined order.
Claim 18
Dependent Claim
19 words
The apparatus recited in claim 12, wherein said converter circuit further comprises a multi-stage flash analog to digital converter.
Claim 19
Dependent Claim
57 words
The apparatus recited in claim 17, wherein said timing control system further comprises means for controlling said first and additional plurality of switches to change state during time periods when said voltage reference in said second inputs of said comparators as a result of switching between stages have essentially no effect on said analog and digital outputs.
Claim 20
Dependent Claim
54 words
The apparatus recited in claim 10, wherein said multi-stage analog to digital converter comprises a second plurality of comparators receiving said analog signal on first inputs of said second plurality of comparators and switches for routing reference voltage levels intermediate of said different voltage references to second inputs of said second plurality of comparators.
Claim 21
Dependent Claim
54 words
The apparatus recited in claim 17, wherein said multi-stage analog to digital converter comprises a second plurality of comparators receiving said analog signal on first inputs of said second plurality of comparators and switches for routing reference voltage levels intermediate of said different voltage references to second inputs of said second plurality of comparators.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-05 | 1998-03-07 | 1998-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-05 | 2002-03-07 | 2002-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-05 | 2006-03-07 | 2006-09-06 | $7700.00 | Window Closed / Lapsed |