Patent US5344790A successfully refreshed from Google Patents.
US5344790A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Making integrated circuit transistor having drain junction offset
Assignee: STMicroelectronics lnc USA
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Filing: 1993-08-31
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Granted: 1994-09-06
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Expires: 2013-08-31
Abstract
Abstract A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.
Inventors
- 👤 Frank R. Bryant
- 👤 Robert L. Hodges
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
115 words
A method for forming an integrated circuit device, comprising the steps of: forming a gate insulating layer over a conductive layer; forming a gate electrode over the gate insulating layer; forming a source sidewall spacer and a drain sidewall spacer alongside opposite vertical edges of the gate electrode; forming a mask over a drain region in the conductive layer; implanting a relatively fast-diffusing dopant into a source region in the conductive layer; removing the mask; implanting a relatively slow-diffusing dopant into the drain region; and annealing the conductive layer causing the relatively fast-diffusing dopant and the relatively slow-diffusing dopant to diffuse into the conductive layer, producing a drain junction offset in the integrated circuit device.
Claim 2
Independent Claim
115 words
A method for forming an integrated circuit device, comprising the steps of: forming a gate insulating layer over a conductive layer; forming a gate electrode over the gate insulating layer; forming a source sidewall spacer and a drain sidewall spacer alongside opposite vertical edges of the gate electrode; forming a mask over a drain region in the conductive layer; implanting a relatively fast-diffusing dopant into a source region in the conductive layer; removing the mask; implanting a relatively slow-diffusing dopant into the drain region; and annealing the conductive layer causing the relatively fast-diffusing dopant and the relatively slow-diffusing dopant to diffuse into the conductive layer, producing a drain junction offset in the integrated circuit device.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein the conductive layer comprises monocrystalline silicon.
Claim 4
Dependent Claim
12 words
The method of claim 1 wherein the conductive layer comprises polycrystalline silicon.
Claim 5
Dependent Claim
20 words
The method of claim 1 wherein the relatively fast-diffusing dopant comprises boron, and wherein the relatively slow-diffusing dopant comprises indium.
Claim 6
Dependent Claim
20 words
The method of claim 1 wherein the relatively fast-diffusing dopant comprises phosphorus, and wherein the relatively slow-diffusing dopant comprises arsenic.
Claim 7
Dependent Claim
20 words
The method of claim 1 wherein the relatively fast-diffusing dopant comprises phosphorus, and wherein the relatively slow-diffusing dopant comprises antimony.
Claim 8
Dependent Claim
32 words
The method of claim 1 wherein the relatively fast-diffusing dopant has an associated fast diffusion rate that is at least twice an associated slow diffusion rate associated with the relatively slow-diffusing dopant.
Claim 9
Dependent Claim
33 words
The method of claim 1 wherein the step of implanting a relatively slow-diffusing dopant into the drain region further comprises implanting a relatively slow-diffusing dopant into the drain region and the source region.
Claim 10
Dependent Claim
69 words
The method of claim 1 wherein the step of annealing the conductive layer causes the relatively fast-diffusing dopant to extend beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causes the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a distance that is less than approximately half the width of the drain sidewall spacer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-05 | 1998-03-07 | 1998-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-05 | 2002-03-07 | 2002-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-05 | 2006-03-07 | 2006-09-06 | $7700.00 | Window Closed / Lapsed |