Patent US5343167A successfully refreshed from Google Patents.
US5343167A
Expired / Lapsed
US
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One-shot control circuit for tracking a voltage-controlled oscillator
Assignee: Silicon Systems Inc
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Filing: 1993-02-03
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Granted: 1994-08-30
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Expires: 2013-02-03
Abstract
Abstract A one-shot control mechanism for ensuring close tracking of one-shot period to VCO period. The one-shot control mechanism provides immunity to data jitter and other spurious phenomena as well as stable and accurate tracking of one-shot period even when the VCO frequency varies from the center frequency of the VCO. The present invention includes a data capture PLL circuit and a frequency reference PLL circuit. The frequency reference PLL circuit provides a control signal to one or more one-shots to control their output pulse duration. Since the frequency reference PLL circuit operates at the expected frequency of data input, a relatively constant relationship may be maintained between the output pulse duration of the one-shots and the period of the VCO output.
Inventors
- 👤 Rodney T. Masumoto
- 👤 Jenn-Gang Chern
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:44
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/07; H03L7/0807
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
93 words
A circuit comprising: a first data input for receiving a data signal; a first phase locked loop (PLL) coupled to said first data input, for tracking said data signal; a frequency reference input for receiving a frequency reference signal; a second PLL coupled to said frequency reference input, for tracking said frequency reference signal and for providing a one-shot duration control signal; and a first one-shot coupled to said second PLL for receiving said one-shot control signal and for providing an first output pulse, said first output pulse dependent on said data signal.
Claim 2
Dependent Claim
93 words
A circuit comprising: a first data input for receiving a data signal; a first phase locked loop (PLL) coupled to said first data input, for tracking said data signal; a frequency reference input for receiving a frequency reference signal; a second PLL coupled to said frequency reference input, for tracking said frequency reference signal and for providing a one-shot duration control signal; and a first one-shot coupled to said second PLL for receiving said one-shot control signal and for providing an first output pulse, said first output pulse dependent on said data signal.
Claim 3
Dependent Claim
19 words
The circuit of claim 1 wherein said first output pulse has a duration dependent on said one-shot control signal.
Claim 4
Dependent Claim
28 words
The circuit of claim 1 further comprising a second one-shot coupled to said second PLL for receiving said one-shot control signal and for providing a second output pulse.
Claim 5
Dependent Claim
20 words
The circuit of claim 3 wherein said first and second output pulses have durations dependent on said one-shot control signal.
Claim 6
Dependent Claim
25 words
The circuit of claim 4 wherein said first one-shot is coupled to said first PLL and wherein said first PLL receives said first output pulse.
Claim 7
Dependent Claim
91 words
A circuit comprising: a first oscillator for producing a first oscillator output; control means coupled to said first oscillator for controlling a period of said first oscillator and for providing a one-shot duration control signal; a first one-shot coupled to said control means for receiving said one-shot control signal and for producing a first output pulse; a second oscillator for producing a second oscillator output signal; comparison means coupled to said second oscillator and to said first one-shot for comparing timing of said second oscillator output signal to said output pulse.
Claim 8
Dependent Claim
91 words
A circuit comprising: a first oscillator for producing a first oscillator output; control means coupled to said first oscillator for controlling a period of said first oscillator and for providing a one-shot duration control signal; a first one-shot coupled to said control means for receiving said one-shot control signal and for producing a first output pulse; a second oscillator for producing a second oscillator output signal; comparison means coupled to said second oscillator and to said first one-shot for comparing timing of said second oscillator output signal to said output pulse.
Claim 9
Dependent Claim
20 words
The circuit of claim 6 wherein said first output pulse has a first duration dependent upon said one-shot control signal.
Claim 10
Dependent Claim
13 words
The circuit of claim 7 wherein said comparison means is a phase detector.
Claim 11
Dependent Claim
40 words
The circuit of claim 8 wherein said first oscillator and said control means are included as elements of a first phase locked loop (PLL) and said second oscillator and said comparison means are included as elements of a second PLL.
Claim 12
Dependent Claim
28 words
The circuit of claim 9 further comprising a second one-shot coupled to said control means for receiving said one-shot control signal and for producing a second output pulse.
Claim 13
Dependent Claim
20 words
The circuit of claim 10 wherein said second output pulse has a second duration dependent upon said one-shot control signal.
Claim 14
Independent Claim
44 words
A method of controlling the duration of a one-shot comprising the steps of: producing a one-shot control signal from within a first phase locked loop (PLL); producing an output pulse dependent upon said one-shot control signal; applying said output pulse to a second PLL.
Claim 15
Independent Claim
44 words
A method of controlling the duration of a one-shot comprising the steps of: producing a one-shot control signal from within a first phase locked loop (PLL); producing an output pulse dependent upon said one-shot control signal; applying said output pulse to a second PLL.
Claim 16
Dependent Claim
47 words
The method of claim 12 wherein said step of producing said output pulse dependent upon said one-shot control signal comprises the steps of: applying said one-shot control signal to a control input of a one-shot and applying a data signal to a data input of said one-shot.
Claim 17
Dependent Claim
33 words
The method of claim 13 wherein said step of applying said output pulse to said second PLL comprises the step of applying said output pulse to a phase comparator of said second PLL.
Claim 18
Dependent Claim
38 words
The method of claim 14 wherein said step of producing said one-shot control signal from within said first PLL comprises the step of producing said one-shot control signal from with a VCO control block of said first PLL.
Claim 19
Dependent Claim
55 words
An integrated circuit comprising: a first PLL circuit block for producing a one-shot control signal; a second PLL circuit block coupled to said first PLL for receiving said one-shot control signal, said second PLL circuit block comprising: a first one-shot for producing a first output having a first duration proportional to said one-shot control signal.
Claim 20
Dependent Claim
55 words
An integrated circuit comprising: a first PLL circuit block for producing a one-shot control signal; a second PLL circuit block coupled to said first PLL for receiving said one-shot control signal, said second PLL circuit block comprising: a first one-shot for producing a first output having a first duration proportional to said one-shot control signal.
Claim 21
Dependent Claim
31 words
The integrated circuit of claim 16 wherein said first PLL circuit block is a frequency reference PLL circuit block and said second PLL circuit block is a data recovery PLL circuit.
Claim 22
Dependent Claim
31 words
The integrated circuit of claim 17 wherein said second PLL circuit further comprises a second one-shot for producing a second output having a second duration proportional to said one-shot control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |