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US5343067A
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High breakdown voltage semiconductor device
Assignee: Toshiba Corp
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Filing: 1992-01-31
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Granted: 1994-08-30
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Expires: 2012-01-31
Abstract
Abstract A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.
Inventors
- 👤 Akio Nakagawa
- 👤 Norio Yasuhara
- 👤 Tomoko Matsudai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:39
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/111; H10D64/112; H10D12/00; H10D12/411; H10D12/421; H10D18/00; H10D18/251; H10D18/40; H10D18/60; H10D18/65; H10D18/655; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/601; H10D30/603; H10D30/605; H10D30/64; H10D30/65; H10D30/657; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D64/115; H10D64/117; H10D64/118; H10D8/00; H10D8/411; H10D84/00; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/061; H10W10/10; H10W10/181; H10W15/00; H10W15/01; H10P90/1914; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
147 words
A high breakdown voltage semiconductor device comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer directly formed on said substrate; an isolation region formed in said high resistance semiconductor layer; an element region formed in said high-resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region of a first conductivity type formed in a central surface portion of said element region; and a second low resistance region of a second conductivity type formed in a peripheral surface portion of said element region and reaching said substrate, a dose of impurities being set in said element region such that a portion of said element region between said first low resistance region and said second low resistance region is completely depleted when voltage is applied between said first and second low resistance regions.
Claim 2
Dependent Claim
147 words
A high breakdown voltage semiconductor device comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer directly formed on said substrate; an isolation region formed in said high resistance semiconductor layer; an element region formed in said high-resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region of a first conductivity type formed in a central surface portion of said element region; and a second low resistance region of a second conductivity type formed in a peripheral surface portion of said element region and reaching said substrate, a dose of impurities being set in said element region such that a portion of said element region between said first low resistance region and said second low resistance region is completely depleted when voltage is applied between said first and second low resistance regions.
Claim 3
Dependent Claim
24 words
The device according to claim 1, wherein said dose of impurities in said element region is 0.1×10 12 to 3×10 12 /cm 2 .
Claim 4
Dependent Claim
33 words
The device according to claim 1, further comprising a third low resistance region of a first conductivity type formed at a boundary surface portion between said isolation region and said low resistance region.
Claim 5
Dependent Claim
16 words
The device according to claim 1, wherein said first low resistance region reaches to said substrate.
Claim 6
Dependent Claim
16 words
The device according to claim 1, wherein said isolation region is formed of an insulating member.
Claim 7
Dependent Claim
16 words
The device according to claim 1, wherein said isolation region is formed of a pn junction.
Claim 8
Dependent Claim
18 words
The device according to claim 1, wherein said insulating layer has a thickness of 1 μm or more.
Claim 9
Dependent Claim
18 words
The device according to claim 1, wherein said insulating layer has a thickness of 2 μm or more.
Claim 10
Dependent Claim
49 words
The device according to claim 1, wherein a distance between the second low resistance region and the insulating layer is a value represented by the √20ε/q.C N (cm) or less. ε: 1.05×10 -12 F/cm q: 1.6×10 -19 (C) C N : impurity concentration of the high resistance semiconductor layer.
Claim 11
Dependent Claim
25 words
The device according to claim 1, wherein said substrate is a semiconductor substrate having an insulating layer directly bonded to said high resistance semiconductor layer.
Claim 12
Dependent Claim
24 words
The device according to claim 1, further comprising a buffer layer of a first conductivity type between said insulating layer and said element region.
Claim 13
Dependent Claim
147 words
A MOS transistor comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer formed on said substrate; an isolation region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region of a first conductivity type formed in said element region and constituting a drain region; a second low resistance region of a second conductivity type formed in said element region; and a source region of a first conductivity type formed in said second low resistance region, wherein a dose of impurities in said element region is set such that a portion of said element region between said source region and said drain region is completely depleted when voltage is applied between said source region and said drain region.
Claim 14
Dependent Claim
147 words
A MOS transistor comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer formed on said substrate; an isolation region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region of a first conductivity type formed in said element region and constituting a drain region; a second low resistance region of a second conductivity type formed in said element region; and a source region of a first conductivity type formed in said second low resistance region, wherein a dose of impurities in said element region is set such that a portion of said element region between said source region and said drain region is completely depleted when voltage is applied between said source region and said drain region.
Claim 15
Dependent Claim
25 words
The device according to claim 12, wherein said substrate is a semiconductor substrate having an insulating layer directly bonded to said high resistance semiconductor layer.
Claim 16
Dependent Claim
16 words
The transistor according to claim 12, wherein said first low resistance region reaches said insulating layer.
Claim 17
Dependent Claim
16 words
The transistor according to claim 12, wherein said second low resistance region reaches said insulating layer.
Claim 18
Dependent Claim
18 words
The transistor according to claim 12, wherein said first and second low resistance regions reach said insulating layer.
Claim 19
Dependent Claim
32 words
The transistor according to claim 12, further comprising a high resistance region in a bottom portion of said high resistance semiconductor layer, said second low resistance region reaches said high resistance region.
Claim 20
Dependent Claim
172 words
A high breakdown voltage semiconductor device comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer formed on said substrate; an isolation region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region of a first conductivity type formed in said element region; and a second low resistance region of a second conductivity type formed in a surface portion of said element region to be separated from said first low resistance region, wherein when voltage is applied between said first low resistance region and said second low resistance region and both potential of said first low resistance region and that of said second low resistance region are higher than a potential of said semiconductor substrate, a channel region of a second conductivity type is formed in the bottom portion of said element region, whereby influence of potential of said semiconductor substrate is shielded.
Claim 21
Dependent Claim
172 words
A high breakdown voltage semiconductor device comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer formed on said substrate; an isolation region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolation region in a lateral direction; a first low resistance region of a first conductivity type formed in said element region; and a second low resistance region of a second conductivity type formed in a surface portion of said element region to be separated from said first low resistance region, wherein when voltage is applied between said first low resistance region and said second low resistance region and both potential of said first low resistance region and that of said second low resistance region are higher than a potential of said semiconductor substrate, a channel region of a second conductivity type is formed in the bottom portion of said element region, whereby influence of potential of said semiconductor substrate is shielded.
Claim 22
Dependent Claim
17 words
The device according to claim 18, wherein said first low resistance region reaches to said insulating layer.
Claim 23
Dependent Claim
39 words
The device according to claim 18, wherein an impurity region having lower impurity concentration than that of said first low resistance region is formed close to or contacting said first low resistance region or said second low resistance region.
Claim 24
Dependent Claim
32 words
The device according to claim 18, wherein a gate insulating layer is formed on a surface of said element region between said first low resistance region and said second low resistance region.
Claim 25
Dependent Claim
19 words
The device according to claim 21, wherein said gate insulating layer has a thickness of 0.3 μm or less.
Claim 26
Dependent Claim
18 words
The device according to claim 21, wherein a high resistance layer is formed on said gate insulating layer.
Claim 27
Dependent Claim
32 words
The device according to claim 18, wherein the high resistance layer is formed on a surface of said element region between said first low resistance region and said second low resistance region.
Claim 28
Dependent Claim
22 words
The device according to claim 18, wherein a dose of impurities in said element region is 1.0×10 10 to 2.0×10 10 .
Claim 29
Dependent Claim
25 words
The device according to claim 18, wherein said substrate is a semiconductor substrate having an insulating layer directly bonded to said high resistance semiconductor layer.
Claim 30
Dependent Claim
175 words
A lateral type insulated gate bipolar transistor comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer formed on said substrate; an isolating region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolated region in a lateral direction; a first low resistance region of a first conductivity type formed in said element region; a second low resistance region of a second conductivity type formed in said first low resistance region and constituting a drain region; a third low resistance region of the second conductivity type formed in said element region; and a fourth low resistance region of the first conductivity type formed in said third low resistance region and constituting a source region; wherein a dose of impurities in said element region is set such that a portion of said element region between said source region and said drain region is completely depleted when voltage is applied between said source region and said drain region.
Claim 31
Dependent Claim
175 words
A lateral type insulated gate bipolar transistor comprising: a substrate, a surface of which is made of an insulating material; a high resistance semiconductor layer formed on said substrate; an isolating region formed in said high resistance semiconductor layer; an element region formed in said high resistance semiconductor layer isolated by said isolated region in a lateral direction; a first low resistance region of a first conductivity type formed in said element region; a second low resistance region of a second conductivity type formed in said first low resistance region and constituting a drain region; a third low resistance region of the second conductivity type formed in said element region; and a fourth low resistance region of the first conductivity type formed in said third low resistance region and constituting a source region; wherein a dose of impurities in said element region is set such that a portion of said element region between said source region and said drain region is completely depleted when voltage is applied between said source region and said drain region.
Claim 32
Dependent Claim
25 words
The device according to claim 27, wherein said substrate is a semiconductor substrate having an insulating layer directly bonded to said high resistance semiconductor layer.
Claim 33
Dependent Claim
29 words
The transistor according to claim 28, wherein said third low resistance region reaches said insulating layer, and said second low resistance region is spaced apart from said insulating layer.
Claim 34
Dependent Claim
16 words
The transistor according to claim 28, wherein said first low resistance region reaches said insulating layer.
Claim 35
Dependent Claim
18 words
The device according to claim 12, wherein said insulating layer has a thickness of 1 μm or more.
Claim 36
Dependent Claim
18 words
The device according to claim 12, wherein said insulating layer has a thickness of 2 μm or more.
Claim 37
Dependent Claim
18 words
The device according to claim 18, wherein said insulating layer has a thickness of 1 μm or more.
Claim 38
Dependent Claim
18 words
The device according to claim 18, wherein said insulating layer has a thickness of 2 μm or more.
Claim 39
Dependent Claim
18 words
The device according to claim 27, wherein said insulating layer has a thickness of 1 μm or more.
Claim 40
Dependent Claim
18 words
The device according to claim 27, wherein said insulating layer has a thickness of 2 μm or more.
References Cited (Backward Citations)
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