Patent US5342480A successfully refreshed from Google Patents.
US5342480A
Expired / Lapsed
US
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Method of manufacturing a semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1993-06-01
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Granted: 1994-08-30
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Expires: 2013-06-01
Abstract
Abstract An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming grooves, to the main surface of a non-active region of a semiconductor substrate or a semiconductor layer, each groove extending into the substrate or layer and forming island regions of the substrate or layer, forming a burying material and a first mask having an etching rate greater than that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of the island regions and in the grooves, such that the film thickness is made virtually uniform for each of the surfaces, forming a second mask on the surface of the first mask, through which the region on each of the island regions is exposed and in which the end of the opening is situated from the end of the island region to the outside of the island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and applying isotropic etching successively to each of the first mask and the burying material by using the second mask as an etching mask, under a condition in which the etching rate for the first mask is greater than that for the burying material.
Inventors
- 👤 Hirotaka Nishizawa
- 👤 Seiichiro Azuma
- 👤 Takayuki Yoshitake
- 👤 Kazuo Tanaka
- 👤 Mikinori Kawaji
- 👤 Sinmei Hirano
- 👤 Toshio Yamada
- 👤 Yasusi Sekine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:16
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
330 words
A method of manufacturing a semiconductor integrated circuit device of forming grooves to a main surface of a non-active region of a semiconductor substrate or semiconductor layer, forming island regions each defined at the periphery thereof by said grooves to a main surface of an active region of said semiconductor substrate or semiconductor layer and insulating and isolating said island regions from each other by a burying material buried in said grooves, comprising: (a) a step of forming grooves to the main surface of the non-active region of said semiconductor substrate or said semiconductor layer, each groove extending from the surface to the direction of the depth thereof and forming island regions each defined at the periphery thereof with said grooves, to the main surface of the active region of said semiconductor substrate or said semiconductor layer, (b) a step of forming a burying material and a first mask having an etching rate greater as compared with that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of said island regions, on the lateral sides and the bottoms of said grooves, such that the film thickness is made virtually uniform for each of the surfaces, (c) a step of forming a second mask on the surface of said first mask, through which the region on each of said island regions is opened and in which the end of the opening is situated from the end of said island region to the outside of said island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and (d) a step of applying isotropic etching successively to each of said first mask and said burying material by using said second mask as an etching mask, under a condition in which the etching rate for the first mask is greater as compared with that for the burying material.
Claim 2
Independent Claim
330 words
A method of manufacturing a semiconductor integrated circuit device of forming grooves to a main surface of a non-active region of a semiconductor substrate or semiconductor layer, forming island regions each defined at the periphery thereof by said grooves to a main surface of an active region of said semiconductor substrate or semiconductor layer and insulating and isolating said island regions from each other by a burying material buried in said grooves, comprising: (a) a step of forming grooves to the main surface of the non-active region of said semiconductor substrate or said semiconductor layer, each groove extending from the surface to the direction of the depth thereof and forming island regions each defined at the periphery thereof with said grooves, to the main surface of the active region of said semiconductor substrate or said semiconductor layer, (b) a step of forming a burying material and a first mask having an etching rate greater as compared with that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of said island regions, on the lateral sides and the bottoms of said grooves, such that the film thickness is made virtually uniform for each of the surfaces, (c) a step of forming a second mask on the surface of said first mask, through which the region on each of said island regions is opened and in which the end of the opening is situated from the end of said island region to the outside of said island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and (d) a step of applying isotropic etching successively to each of said first mask and said burying material by using said second mask as an etching mask, under a condition in which the etching rate for the first mask is greater as compared with that for the burying material.
Claim 3
Dependent Claim
149 words
A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein the step of forming the grooves to the non-active region of the semiconductor substrate or the semiconductor layer comprises a step of forming said grooves by applying anisotropic etching to the main surface of the non-active region of said semiconductor substrate or said semiconductor layer by using a third mask formed on the main surface of the active region of said semiconductor substrate or said semiconductor layer as an etching mask and, subsequent to the step of forming the groove, introducing an impurity at a higher concentration as compared with an impurity concentration of said semiconductor substrate or said semiconductor layer to the bottom of said grooves on the main surface of said semiconductor substrate or said semiconductor layer by using said third mask as an impurity introduction mask, thereby forming a semiconductor region.
Claim 4
Dependent Claim
103 words
A method of manufacturing a semiconductor integrated circuit device as defined in claim 2, wherein the step of forming the semiconductor region to the bottom of the grooves on the main surface of the semiconductor substrate or said semiconductor layer comprises a step of introducing an impurity at a higher concentration as compared with that in said semiconductor substrate or said semiconductor layer to the bottom of said grooves on the main surface of said semiconductor substrate or said semiconductor layer, then applying an extending diffusion treatment to said impurity at high concentration and joining the high concentration impurity in said island regions.
Claim 5
Independent Claim
229 words
A method of manufacturing a semiconductor integrated circuit device of forming grooves to a main surface of an inactive region of a semiconductor substrate or a semiconductor layer, forming island regions each defined at the periphery thereof by said grooves to a main surface of an active region of the said semiconductor substrate or said semiconductor layer and then insulating and isolating said island regions from each other by a burying material buried in said grooves, comprising: (e) a step of forming an insulating film on the upper surface and the lateral side of said island regions such that the film thickness is made substantially uniform to each of the surfaces, (f) a step of forming a semiconductor region by introducing an impurity of a conduction type identical with that of said semiconductor substrate or said semiconductor layer and at a higher concentration as compared with the impurity concentration therein at a shoulder region where the lateral side and the upper surface of said island region intersects on the main surface of said semiconductor region or said semiconductor layer, through said insulating film by using an ion implantation method at an angle inclined relative to the upper surface of said island region, and (i) a step of forming MISFET to the upper surface of said island regions on the main surface of said semiconductor region or said semiconductor layer.
Claim 6
Independent Claim
229 words
A method of manufacturing a semiconductor integrated circuit device of forming grooves to a main surface of an inactive region of a semiconductor substrate or a semiconductor layer, forming island regions each defined at the periphery thereof by said grooves to a main surface of an active region of the said semiconductor substrate or said semiconductor layer and then insulating and isolating said island regions from each other by a burying material buried in said grooves, comprising: (e) a step of forming an insulating film on the upper surface and the lateral side of said island regions such that the film thickness is made substantially uniform to each of the surfaces, (f) a step of forming a semiconductor region by introducing an impurity of a conduction type identical with that of said semiconductor substrate or said semiconductor layer and at a higher concentration as compared with the impurity concentration therein at a shoulder region where the lateral side and the upper surface of said island region intersects on the main surface of said semiconductor region or said semiconductor layer, through said insulating film by using an ion implantation method at an angle inclined relative to the upper surface of said island region, and (i) a step of forming MISFET to the upper surface of said island regions on the main surface of said semiconductor region or said semiconductor layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |