Data output circuit with minimum power source noise

Claim 2

An integrated circuit comprising a plurality of data output circuits, each of which is responsive to data signals complementary to each other for outputting data corresponding to said data signals: each of said plurality of data output circuits comprising: an output terminal for outputting the data; a first output transistor comprising a path of controllable conductivity whose one electrode is connected to said output terminal, and a control electrode for controlling said path of controllable conductivity in response to a first signal; a second output transistor comprising a path of controllable conductivity whose one electrode for controlling said path of controllable conductivity in response to a second signal complementary to the first signal; a first switch transistor comprising a path of controllable conductivity having one electrode connected to the other electrode of the path of controllable conductivity of said first output transistor and another electrode connected to a first power source, and a control electrode for rendering said path of controllable conductivity of said first switch transistor conductive in response to a first switch signal; and a first capacitor having one electrode connected to another electrode of the path of controllable conductivity of said first output transistor and another electrode connected to a second power source; said integrated circuit further comprising a control circuit for receiving a control signal which occurs after the first signal, delaying said control signal a predetermined period of time to produce the first switch signal, and feeding said first switch signal to said first switch transistor of each of said plurality of data output circuits.

Claim 3

An integrated circuit in accordance with claim 1, wherein each of said plurality of data output circuits further comprises: a second switch transistor having a path of controllable conductivity connected at one electrode to another electrode of the path of controllable conductivity of said second output transistor and at another electrode to said second power source, and a control electrode for rendering said path of controllable conductivity conductive in response to a second switch signal; and a second capacitor having one electrode connected to the other electrode of the path of controllable conductivity of said second output transistor and another electrode connected to said first power source; said control circuit delaying the control signal the predetermined period f time to produce the second switch signal complementary to the first switch signal and feeding said second switch signal to said second switch transistor of each of said plurality of data output circuits.

Claim 4

An integrated circuit in accordance with claim 1, wherein each of said plurality of data output circuits further comprises a latch circuit for receiving the data signals, holding said data signals in response to the control signal, and applying the first and second signals respectively to said control electrodes of said first and second output transistors in response to said data signals.

Claim 5

A data output circuit comprising: an output terminal for outputting data; a first output transistor having a first electrode, a second electrode connected to said output terminal and a first control electrode for receiving a first control signal, the first control signal being in a first logic level in a first period and said first output transistor being in a conductive state when the first control electrode receives the first control signal in the first logic level; a second output transistor having a third electrode connected to said output terminal, a fourth electrode for receiving a voltage of a second level thereto and second control electrode for receiving a second control signal, the second control signal being in the first logic level in a second period different from the first period and said second output transistor being in its conductive state when the second control electrode receives the second control signal in the first logic level; a first switch transistor having a fifth electrode connected to said first electrode, a sixth electrode for receiving a voltage of a first level thereto and a third control electrode for receiving a first switch signal, the first switch signal being in a second logic level in a third and a fourth period, the third period corresponding to a preceding portion of the first period and the fourth period corresponding to a preceding portion of the second period and said first switch transistor being in a non-conductive state only when said third control electrode receives the first switch signal in the second logic level; and a first capacitor having a seventh electrode for applying the voltage of the second level and an eighth electrode connected to said first electrode.

Claim 6

A data output circuit comprising: an output terminal for outputting data; a first output transistor having a first electrode, a second electrode connected to said output terminal and a first control electrode for receiving a first control signal, the first control signal being in a first logic level in a first period and said first output transistor being in a conductive state when the first control electrode receives the first control signal in the first logic level; a second output transistor having a third electrode connected to said output terminal, a fourth electrode for receiving a voltage of a second level thereto and second control electrode for receiving a second control signal, the second control signal being in the first logic level in a second period different from the first period and said second output transistor being in its conductive state when the second control electrode receives the second control signal in the first logic level; a first switch transistor having a fifth electrode connected to said first electrode, a sixth electrode for receiving a voltage of a first level thereto and a third control electrode for receiving a first switch signal, the first switch signal being in a second logic level in a third and a fourth period, the third period corresponding to a preceding portion of the first period and the fourth period corresponding to a preceding portion of the second period and said first switch transistor being in a non-conductive state only when said third control electrode receives the first switch signal in the second logic level; and a first capacitor having a seventh electrode for applying the voltage of the second level and an eighth electrode connected to said first electrode.

Claim 7

A data output circuit in accordance with claim 4, further comprising: a second switch transistor having a ninth electrode connected to said fourth electrode, a tenth electrode for receiving the voltage of the second level thereto and a fourth control electrode for receiving a second switch signal, the second switch signal being in the first logic level in the third and fourth period and said second switch transistor being in the non-conductive state only when said fourth control electrode receives the second switch signal in the first logic level; a second capacitor having an eleventh electrode for applying the voltage of the second level and twelfth electrode connected to said fourth electrode.

Claim 8

A data output circuit in accordance with claim 5, further comprising a latch circuit for receiving data signals complementary to each other, holding the data signals in response to a third control signal, and applying the first and second control signals to, respectively, said first and second control electrodes in association with the data signals.

Claim 9

A data output circuit in accordance with claim 5, further comprising a control circuit responsive to the third control signal for delaying said third control signal a predetermined period of time to thereby produce the first and second switch signals.

Claim 10

A data output circuit in accordance with claim 4, wherein the third period simultaneously begins when the first period begins and ends before the first period ends.

Claim 11

A data output circuit in accordance with claim 4, wherein the fourth period simultaneously begins when the second period begins and ends before the second period ends.

Claim 12

A data output circuit comprising: an output terminal for outputting data; a first voltage level circuit outputting a voltage of a first level to said output terminal in a following portion of a first period; said first voltage level circuit comprising: a first output transistor having an output electrode connected to said output terminal; a first switch transistor having an output electrode connected to an input electrode of said first output transistor and to a second power source through a capacitor, and an input electrode connected to a first power source; a second voltage level circuit outputting a voltage of a second level to said output terminal in complement to said first voltage level circuit in a preceding portion of said first period; said second voltage level circuit comprising: a second output transistor having an output electrode connected to said output terminal; a second switch transistor having an output electrode connected to an input electrode of said second output transistor and to the first power source through a capacitor, and an input electrode connected to the second power source; a latch circuit including a pair of tri-input NAND gates having complementary output gates respectively connected to control electrodes of said first and second output transistors through an inverter for respectively controlling both said output transistors, input gates commonly connected so as to output an output enable signal and other input gates being for respectively receiving complementary data; a switch control circuit having a pair of output electrodes respectively connected to switch control electrodes of said first and second switch transistors; and said switch control circuit receiving the output enable signal from said latch circuit and complementarily switching said switch transistors.

Claim 13

A data output circuit comprising: an output terminal for outputting data; a first voltage level circuit outputting a voltage of a first level to said output terminal in a following portion of a first period; said first voltage level circuit comprising: a first output transistor having an output electrode connected to said output terminal; a first switch transistor having an output electrode connected to an input electrode of said first output transistor and to a second power source through a capacitor, and an input electrode connected to a first power source; a second voltage level circuit outputting a voltage of a second level to said output terminal in complement to said first voltage level circuit in a preceding portion of said first period; said second voltage level circuit comprising: a second output transistor having an output electrode connected to said output terminal; a second switch transistor having an output electrode connected to an input electrode of said second output transistor and to the first power source through a capacitor, and an input electrode connected to the second power source; a latch circuit including a pair of tri-input NAND gates having complementary output gates respectively connected to control electrodes of said first and second output transistors through an inverter for respectively controlling both said output transistors, input gates commonly connected so as to output an output enable signal and other input gates being for respectively receiving complementary data; a switch control circuit having a pair of output electrodes respectively connected to switch control electrodes of said first and second switch transistors; and said switch control circuit receiving the output enable signal from said latch circuit and complementarily switching said switch transistors.

Claim 14

A data output circuit in accordance with claim 10, wherein said output transistor outputs the voltage of the second level in the preceding portion of said first period.