Input buffer circuit with deglitch method and apparatus

Claim 3

The method of claim 1, further comprising the steps of: switching in a second transition from said HI to said LO output state when the input signal falls successively through said HI and LO threshold levels, inhibiting a reversion to said HI output state, for a predetermined fixed delay period following said second transition that is no greater than the minimum duration for a HI input state, unless said input signal rises above a boosted HI threshold level that is greater than said HI threshold level, and thereafter inhibiting a reversion to said HI output state unless said input signal rises above said HI threshold level.

Claim 4

The method of claim 2, wherein the delay periods following said first and second transitions are equal.

Claim 5

The method of claim 2, wherein said HI and LO threshold levels are restricted to a predetermined window of threshold levels over predetermined process, temperature and power supply ranges, and said boosted HI and boosted LO threshold levels are outside are window.

Claim 6

In a Schmitt trigger circuit that includes means for switching from a LO to a HI output state in response to an input signal rising above a HI threshold level, and means for switching from a HI to a LO output state in response to the input signal falling below a LO threshold level that is offset by a hysteresis amount below said HI threshold level, the improvement comprising: means connected to said LO to HI output state switching means for temporarily increasing said hysteresis amount in response to the input signal initiating an output state transition, and means connected to said means for temporarily increasing said hysteresis amount for terminating said increase in the hysteresis amount after a predetermined fixed delay period that is independent of the input signal level.

Claim 7

In a Schmitt trigger circuit that includes means for switching from a LO to a HI output state in response to an input signal rising above a HI threshold level, and means for switching from a HI to a LO output state in response to the input signal falling below a LO threshold level that is offset by a hysteresis amount below said HI threshold level, the improvement comprising: means connected to said LO to HI output state switching means for temporarily increasing said hysteresis amount in response to the input signal initiating an output state transition, and means connected to said means for temporarily increasing said hysteresis amount for terminating said increase in the hysteresis amount after a predetermined fixed delay period that is independent of the input signal level.

Claim 8

The Schmitt trigger circuit of claim 5, for use with an alternating input signal that remains LO for at least a known minimum period and then remains HI for at least a known minimum period, wherein said fixed predetermined delay period is no greater than said minimum periods.

Claim 9

The Schmitt trigger circuit of claim 6, said Schmitt trigger circuit being limited to switching between HI and LO output states at threshold levels that are within a predetermined threshold level window, wherein said HI and LO threshold levels are within said window in the absence of said offset and at least one of said HI and LO threshold levels is outside said window in the presence of said offset.

Claim 10

The Schmitt trigger circuit of claim 5, wherein said means for temporarily increasing the hysteresis threshold offset increases said offset for both a transition from a LO to a HI and from a HI to a LO output state.

Claim 11

The Schmitt trigger circuit of claim 8, wherein said terminating means terminates said increases in the hysteresis threshold offset after equal delay periods for transitions from LO to HI and from HI to LO output states.

Claim 12

The Schmitt trigger circuit of claim 8, wherein the amount of increase in said hysteresis threshold offset is different for a transition from a LO to a HI output state than for a transition from a HI to a LO output state.

Claim 13

A buffer circuit for an input signal that alternates between LO and HI input states, with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, comprising: a conversion circuit for converting said input signal to one of a plurality of output states, including threshold means for converting from a first to a second output state in response to a first transition at which the input signal crosses a first fixed threshold level in a first direction, a first hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a first transient threshold level that is offset from said first fixed threshold level by a first boosted hysteresis amount in a direction opposite to said first input signal direction, said threshold adjustment preventing a reversion back to said first output state until the input signal has crossed both said first fixed and said first transient threshold levels in said opposite direction, and delay means for disabling said first hysteresis circuit at the end of a first fixed predetermined delay period after said first transition, said first delay period being no greater than the minimum input signal period following said first transition.

Claim 14

A buffer circuit for an input signal that alternates between LO and HI input states, with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, comprising: a conversion circuit for converting said input signal to one of a plurality of output states, including threshold means for converting from a first to a second output state in response to a first transition at which the input signal crosses a first fixed threshold level in a first direction, a first hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a first transient threshold level that is offset from said first fixed threshold level by a first boosted hysteresis amount in a direction opposite to said first input signal direction, said threshold adjustment preventing a reversion back to said first output state until the input signal has crossed both said first fixed and said first transient threshold levels in said opposite direction, and delay means for disabling said first hysteresis circuit at the end of a first fixed predetermined delay period after said first transition, said first delay period being no greater than the minimum input signal period following said first transition.

Claim 15

The buffer circuit of claim 11, further comprising a second hysteresis circuit connected to said conversion circuit, for adjusting said first fixed threshold level, in response to said first transition, to a second fixed threshold level that is offset from said first fixed threshold level in the same direction as, but by a lesser hysteresis amount than, said first transient threshold level, said second hysteresis circuit being substantially continuously operable but overridden by said first hysteresis circuit during said delay period.

Claim 16

A buffer circuit for an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, comprising: a conversion circuit for converting said input signal to one of a plurality of output states, including threshold means for converting from a first to a second output state in response to a first transition at which the input signal crosses a first fixed threshold level in a first direction, a first hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a first transient threshold level that is offset from said first fixed threshold level by a first boosted hysteresis amount in a direction opposite to said first input signal direction, said threshold adjustment preventing a reversion back to said first output state until the input signal has crossed both said first and said first transient threshold levels in said opposite direction, delay means for disabling said first hysteresis circuit at the end of a first fixed predetermined delay period after said first transition, said first delay period being no greater than the minimum input signal period following said first transition, and a second hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a second fixed threshold level that is offset from said first fixed threshold level in the same direction as, but by a lesser hysteresis amount than, said first transient threshold level, said second hysteresis circuit being substantially continuously operable but overridden by said first hysteresis circuit during said delay period, wherein said buffer circuit operates with a predetermined threshold limit to which its conversion threshold level is limited over predetermined process, temperature and power supply ranges, wherein said first and second fixed threshold levels are inside but said first transient threshold level is outside said threshold limit.

Claim 17

A buffer circuit for an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, comprising: a conversion circuit for converting said input signal to one of a plurality of output states, including threshold means for converting from a first to a second output state in response to a first transition at which the input signal crosses a first fixed threshold level in a first direction, a first hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a first transient threshold level that is offset from said first fixed threshold level by a first boosted hysteresis amount in a direction opposite to said first input signal direction, said threshold adjustment preventing a reversion back to said first output state until the input signal has crossed both said first and said first transient threshold levels in said opposite direction, delay means for disabling said first hysteresis circuit at the end of a first fixed predetermined delay period after said first transition, said first delay period being no greater than the minimum input signal period following said first transition, and a second hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a second fixed threshold level that is offset from said first fixed threshold level in the same direction as, but by a lesser hysteresis amount than, said first transient threshold level, said second hysteresis circuit being substantially continuously operable but overridden by said first hysteresis circuit during said delay period, wherein said buffer circuit operates with a predetermined threshold limit to which its conversion threshold level is limited over predetermined process, temperature and power supply ranges, wherein said first and second fixed threshold levels are inside but said first transient threshold level is outside said threshold limit.

Claim 18

A buffer circuit for an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, comprising: a conversion circuit for converting said input signal to one of a plurality of output states, including threshold means for converting from a first to a second output state in response to a first transition at which the input signal crosses a first fixed threshold level in a first direction, said conversion circuit converting from said second to said first output state in response to a second transition at which the input signal crosses said second fixed threshold level in a direction opposite said first input signal direction, a first hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a first transient threshold level that is offset from said first fixed threshold level by a first boosted hysteresis amount in a direction opposite to said first input signal direction, said threshold adjustment preventing a reversion back to said first output state until the input signal has crossed both said first fixed and said first transient threshold levels in said opposite direction, delay means for disabling said first hysteresis circuit at the end of a first predetermined delay period after said first transition, said first delay period being no greater than the minimum HI signal period following a first transition from a LO to a HI input state, and no greater than the minimum LO signal period following a first transition from a HI to a LO input state, a second hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a second fixed threshold level that is offset from said first fixed threshold level in the same direction as, but by a lesser hysteresis amount than, said first transient threshold level, said second hysteresis circuit being substantially continuously operable but overridden by said first hysteresis circuit during said delay period, and a complementary first hysteresis circuit for adjusting said second fixed threshold level, in response to said second transition, to a second transient threshold level by a second boosted hysteresis amount in a direction opposite to said first direction, said second fixed threshold adjustment preventing a reversion back to said second output state until the input signal has crossed both said second fixed and second transient threshold levels in said first direction, and said delay means disabling said complementary first hysteresis circuit at the end of a second fixed predetermined delay period after said second transition, said second delay period being no greater than the minimum LO signal period following a second transition from a HI to LO input state, and no greater than the minimum HI signal period following a second transition from a LO to a HI input state.

Claim 19

A buffer circuit for an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, comprising: a conversion circuit for converting said input signal to one of a plurality of output states, including threshold means for converting from a first to a second output state in response to a first transition at which the input signal crosses a first fixed threshold level in a first direction, said conversion circuit converting from said second to said first output state in response to a second transition at which the input signal crosses said second fixed threshold level in a direction opposite said first input signal direction, a first hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a first transient threshold level that is offset from said first fixed threshold level by a first boosted hysteresis amount in a direction opposite to said first input signal direction, said threshold adjustment preventing a reversion back to said first output state until the input signal has crossed both said first fixed and said first transient threshold levels in said opposite direction, delay means for disabling said first hysteresis circuit at the end of a first predetermined delay period after said first transition, said first delay period being no greater than the minimum HI signal period following a first transition from a LO to a HI input state, and no greater than the minimum LO signal period following a first transition from a HI to a LO input state, a second hysteresis circuit connected to said conversion circuit for adjusting said first fixed threshold level, in response to said first transition, to a second fixed threshold level that is offset from said first fixed threshold level in the same direction as, but by a lesser hysteresis amount than, said first transient threshold level, said second hysteresis circuit being substantially continuously operable but overridden by said first hysteresis circuit during said delay period, and a complementary first hysteresis circuit for adjusting said second fixed threshold level, in response to said second transition, to a second transient threshold level by a second boosted hysteresis amount in a direction opposite to said first direction, said second fixed threshold adjustment preventing a reversion back to said second output state until the input signal has crossed both said second fixed and second transient threshold levels in said first direction, and said delay means disabling said complementary first hysteresis circuit at the end of a second fixed predetermined delay period after said second transition, said second delay period being no greater than the minimum LO signal period following a second transition from a HI to LO input state, and no greater than the minimum HI signal period following a second transition from a LO to a HI input state.

Claim 20

The buffer circuit of claim 14, further comprising a complementary second hysteresis circuit for adjusting said second fixed threshold level, in response to said second transition, back to said first fixed threshold level, said complementary second hysteresis circuit being substantially continuously operable but overridden by said complementary first hysteresis circuit during said second delay period.

Claim 21

The buffer circuit of claim 15, said buffer circuit operating within a predetermined window of threshold levels to which its first and second transition levels are limited over predetermined process, temperature and power supply ranges, wherein said first and second fixed threshold levels are inside but said first and second transient threshold levels are outside said window.

Claim 22

The buffer circuit of claim 15, wherein said delay means provides substantially equal first and second delay periods.

Claim 23

A Schmitt trigger circuit, comprising: an input terminal for receiving an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, an internal output line, a pair of PMOS trigger transistors connected with their source-drain circuits in series between a high voltage reference and said internal output line, a pair of NMOS trigger transistors connected with their source-drain circuits in series between said internal output line and a low voltage reference, means for applying an input signal at said input terminal to the gates of said PMOS and NMOS trigger transistors, a larger PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of the source-drain circuits of said PMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor, a larger NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of the source-drain circuits of said NMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor, a smaller hysteresis transistor means having a source-drain circuit connected between a voltage reference and the junction of the source-drain circuits of at least one of said pairs of trigger transistors, and its gate connected to said internal output line, said smaller hysteresis transistor means being smaller than said larger hysteresis transistors and providing a lower level of hysteresis, a delay circuit for generating a predetermined fixed delay period in response to the Schmitt trigger circuit switching HI or LO, said delay period being no greater than said known minimum HI signal period following the Schmitt trigger circuit switching HI, and no greater than said known minimum LO signal period following the Schmitt trigger circuit switching LO, said delay circuit controlling said switch circuits to disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched HI, and to disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched LO, and an inverter connected to said internal output line to provide a Schmitt trigger output.

Claim 24

A Schmitt trigger circuit, comprising: an input terminal for receiving an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, an internal output line, a pair of PMOS trigger transistors connected with their source-drain circuits in series between a high voltage reference and said internal output line, a pair of NMOS trigger transistors connected with their source-drain circuits in series between said internal output line and a low voltage reference, means for applying an input signal at said input terminal to the gates of said PMOS and NMOS trigger transistors, a larger PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of the source-drain circuits of said PMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor, a larger NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of the source-drain circuits of said NMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor, a smaller hysteresis transistor means having a source-drain circuit connected between a voltage reference and the junction of the source-drain circuits of at least one of said pairs of trigger transistors, and its gate connected to said internal output line, said smaller hysteresis transistor means being smaller than said larger hysteresis transistors and providing a lower level of hysteresis, a delay circuit for generating a predetermined fixed delay period in response to the Schmitt trigger circuit switching HI or LO, said delay period being no greater than said known minimum HI signal period following the Schmitt trigger circuit switching HI, and no greater than said known minimum LO signal period following the Schmitt trigger circuit switching LO, said delay circuit controlling said switch circuits to disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched HI, and to disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched LO, and an inverter connected to said internal output line to provide a Schmitt trigger output.

Claim 25

The Schmitt trigger circuit of claim 18, said smaller hysteresis transistor means comprising: a smaller PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of said PMOS trigger transistors, and its gate connected to said internal output line, said smaller PMOS hysteresis transistor being smaller than said larger PMOS hysteresis transistor and providing a lower level of hysteresis than said larger PMOS hysteresis transistor when the Schmitt trigger circuit has switched HI, and a smaller NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of said NMOS trigger transistors, and its gate connected to said internal output line, said smaller NMOS hysteresis transistor being smaller than said larger NMOS hysteresis transistor and providing a lower level of hysteresis than said larger NMOS hysteresis transistor when the Schmitt trigger circuit has switched LO.

Claim 26

The Schmitt trigger circuit of claim 19, wherein said larger PMOS and NMOS hysteresis transistors have their source-drain circuits connected in parallel with the source-drain circuits of said smaller PMOS and NMOS hysteresis transistors, respectively, and the switch circuits for said larger PMOS and NMOS hysteresis transistors are connected to apply enabling and disabling signals to the gates of their respective larger hysteresis transistors.

Claim 27

The Schmitt trigger circuit of claim 20, said switch circuits including respective NAND or NOR gates connected to receive inputs from said internal output line and from said delay circuit to control the switching states of the switch circuits.

Claim 28

The Schmitt trigger circuit of claim 21, said switch circuits for said larger PMOS hysteresis transistor comprising a NAND gate that is connected to receive an inverted input from said internal output line and a noninverted input from said delay circuit, and has its output connected to the gate of said larger PMOS hysteresis transistor.

Claim 29

The Schmitt trigger circuit of claim 21, said switch circuits for said larger NMOS hysteresis transistor comprising a NOR gate that is connected to receive an inverted input from said internal output line and a noninverted input from said delay circuit, and has its output connected to the gate of said larger NMOS hysteresis transistor.

Claim 30

A Schmitt trigger circuit, comprising: an input terminal for receiving an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, an internal output line, a pair of PMOS trigger transistors connected with their source-drain circuits in series between a high voltage reference and said internal output line, a pair of NMOS trigger transistors connected with their source-drain circuits in series between said internal output line and a low voltage reference, means for applying an input signal at said input terminal to the gates of said PMOS and NMOS trigger transistors, a larger PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of the source-drain circuits of said PMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor, a larger NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of the source-drain circuits of said NMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor, a smaller hysteresis transistor means having a source-drain circuit connected between a voltage reference and the junction of the source-drain circuits of at least one of said pairs of trigger transistors, and its gate connected to said internal output line, said smaller hysteresis transistor means being smaller than said larger hysteresis transistors and providing a lower level of hysteresis, a delay circuit for generating a predetermined fixed delay period in response to the Schmitt trigger circuit switching HI or LO, said delay period being no greater than said known minimum HI signal period following the Schmitt trigger circuit switching HI, and no greater than said known minimum LO signal period following the Schmitt trigger circuit switching LO, said delay circuit controlling said switch circuits to disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched HI, and to disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched LO, and an inverter connected to said internal output line to provide a Schmitt trigger output, said smaller hysteresis transistor means comprising: a smaller PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of said PMOS trigger transistors, and its gate connected to said internal output line, said smaller PMOS hysteresis transistor being smaller than said larger PMOS hysteresis transistor and providing a lower level of hysteresis than said larger PMOS hysteresis transistor when the Schmitt trigger circuit has switched HI, and a smaller NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of said NMOS trigger transistors, and its gate connected to said internal output line, said smaller NMOS hysteresis transistor being smaller than said larger NMOS hysteresis transistor and providing a lower level of hysteresis than said larger NMOS hysteresis transistor when the Schmitt trigger circuit has switched LO, said larger PMOS and NMOS hysteresis transistors having their source-drain circuits connected in parallel with the source-drain circuits of said smaller PMOS and NMOS hysteresis transistors, respectively, and the switch circuits for said larger PMOS and NMOS hysteresis transistors being connected to apply enabling and disabling signals to the gates of their respective larger hysteresis transistors, said switch circuits comprising respective logic negation gates connected to receive inputs from said internal output line and from said delay circuit, and said switch circuit for said larger NMOS hysteresis transistor comprising a NOR gate that is connected to receive an inverted input from said internal output line and a noninverted input from said delay circuit, and has its output connected to the gate of said larger NMOS hysteresis transistor, wherein said delay circuit generates substantially equal delay periods for said Schmitt trigger circuit switching.

Claim 31

A Schmitt trigger circuit, comprising: an input terminal for receiving an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, an internal output line, a pair of PMOS trigger transistors connected with their source-drain circuits in series between a high voltage reference and said internal output line, a pair of NMOS trigger transistors connected with their source-drain circuits in series between said internal output line and a low voltage reference, means for applying an input signal at said input terminal to the gates of said PMOS and NMOS trigger transistors, a larger PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of the source-drain circuits of said PMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor, a larger NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of the source-drain circuits of said NMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor, a smaller hysteresis transistor means having a source-drain circuit connected between a voltage reference and the junction of the source-drain circuits of at least one of said pairs of trigger transistors, and its gate connected to said internal output line, said smaller hysteresis transistor means being smaller than said larger hysteresis transistors and providing a lower level of hysteresis, a delay circuit for generating a predetermined fixed delay period in response to the Schmitt trigger circuit switching HI or LO, said delay period being no greater than said known minimum HI signal period following the Schmitt trigger circuit switching HI, and no greater than said known minimum LO signal period following the Schmitt trigger circuit switching LO, said delay circuit controlling said switch circuits to disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched HI, and to disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched LO, and an inverter connected to said internal output line to provide a Schmitt trigger output, said smaller hysteresis transistor means comprising: a smaller PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of said PMOS trigger transistors, and its gate connected to said internal output line, said smaller PMOS hysteresis transistor being smaller than said larger PMOS hysteresis transistor and providing a lower level of hysteresis than said larger PMOS hysteresis transistor when the Schmitt trigger circuit has switched HI, and a smaller NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of said NMOS trigger transistors, and its gate connected to said internal output line, said smaller NMOS hysteresis transistor being smaller than said larger NMOS hysteresis transistor and providing a lower level of hysteresis than said larger NMOS hysteresis transistor when the Schmitt trigger circuit has switched LO, said larger PMOS and NMOS hysteresis transistors having their source-drain circuits connected in parallel with the source-drain circuits of said smaller PMOS and NMOS hysteresis transistors, respectively, and the switch circuits for said larger PMOS and NMOS hysteresis transistors being connected to apply enabling and disabling signals to the gates of their respective larger hysteresis transistors, said switch circuits comprising respective logic negation gates connected to receive inputs from said internal output line and from said delay circuit, and said switch circuit for said larger NMOS hysteresis transistor comprising a NOR gate that is connected to receive an inverted input from said internal output line and a noninverted input from said delay circuit, and has its output connected to the gate of said larger NMOS hysteresis transistor, wherein said delay circuit generates substantially equal delay periods for said Schmitt trigger circuit switching.

Claim 32

The Schmitt trigger circuit of claim 24, wherein a common inverter is used to provide the inverted input signals for said NAND and NOR gates, and said delay circuit is also connected to receive an input from said common inverter, said delay circuit comprising in sequence from said common inverter a first inverter, a first charging capacitor connected between the output of the first inverter and a ground reference, a second inverter, a second charging capacitor connected between the output of the second inverter and said ground reference, and a third inverter.

Claim 33

A Schmitt trigger circuit, comprising: an input terminal for receiving an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, an internal output line, a pair of PMOS trigger transistors connected with their source-drain circuits in series between a high voltage reference and said internal output line, a pair of NMOS trigger transistors connected with their source-drain circuits in series between said internal output line and a low voltage reference, means for applying an input signal at said input terminal to the gates of said PMOS and NMOS trigger transistors, a larger PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of the source-drain circuits of said PMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor, a larger NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of the source-drain circuits of said NMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor, a smaller hysteresis transistor means having a source-drain circuit connected between a voltage reference and the junction of the source-drain circuits of at least one of said pairs of trigger transistors, and its gate connected to said internal output line, said smaller hysteresis transistor means being smaller than said larger hysteresis transistors and providing a lower level of hysteresis, a delay circuit for generating a predetermined fixed delay period in response to the Schmitt trigger circuit switching HI or LO, said delay period being no greater than said known minimum HI signal period following the Schmitt trigger circuit switching HI, and no greater than said known minimum LO signal period following the Schmitt trigger circuit switching LO, said delay circuit controlling said switch circuits to disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched HI, and to disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched LO, and an inverter connected to said internal output line to provide a Schmitt trigger output, wherein said larger PMOS and NMOS hysteresis transistors have their gates connected to said internal output line, with their respective switch circuits connected in their source-drain circuits.

Claim 34

A Schmitt trigger circuit, comprising: an input terminal for receiving an input signal that alternates between LO and HI input states with the input signal remaining LO for at least a known minimum period and then remaining HI for at least a known minimum period, an internal output line, a pair of PMOS trigger transistors connected with their source-drain circuits in series between a high voltage reference and said internal output line, a pair of NMOS trigger transistors connected with their source-drain circuits in series between said internal output line and a low voltage reference, means for applying an input signal at said input terminal to the gates of said PMOS and NMOS trigger transistors, a larger PMOS hysteresis transistor having its source-drain circuit connected between a low voltage reference and the junction of the source-drain circuits of said PMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor, a larger NMOS hysteresis transistor having its source-drain circuit connected between a high voltage reference and the junction of the source-drain circuits of said NMOS trigger transistors, a switch circuit connected to selectively enable or disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor, a smaller hysteresis transistor means having a source-drain circuit connected between a voltage reference and the junction of the source-drain circuits of at least one of said pairs of trigger transistors, and its gate connected to said internal output line, said smaller hysteresis transistor means being smaller than said larger hysteresis transistors and providing a lower level of hysteresis, a delay circuit for generating a predetermined fixed delay period in response to the Schmitt trigger circuit switching HI or LO, said delay period being no greater than said known minimum HI signal period following the Schmitt trigger circuit switching HI, and no greater than said known minimum LO signal period following the Schmitt trigger circuit switching LO, said delay circuit controlling said switch circuits to disable current flow through the source-drain circuit of said larger PMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched HI, and to disable current flow through the source-drain circuit of said larger NMOS hysteresis transistor at the end of said delay period after the Schmitt trigger circuit has switched LO, and an inverter connected to said internal output line to provide a Schmitt trigger output, wherein said larger PMOS and NMOS hysteresis transistors have their gates connected to said internal output line, with their respective switch circuits connected in their source-drain circuits.

Claim 35

The Schmitt trigger circuit of claim 26, said switch circuits for said larger PMOS and NMOS hysteresis transistors comprising respective NMOS and PMOS switch transistors having their source-drain circuits connected in the source drain circuits for their respective larger hysteresis transistors, and respective logic circuits interfacing between said delay circuit and the gates of their respective switch transistors.

Claim 36

The Schmitt trigger circuit of claim 27, the logic circuit for each switch circuit comprising a respective negation gate connected to receive inputs from said internal output line and from said delay circuit, and to provide control signals to the gate of its respective switch transistor.

Claim 37

The Schmitt trigger circuit of claim 28, wherein the logic circuits for said NMOS and PMOS switch transistors respectively comprise a NOR gate and a NAND gate connected to receive noninverted inputs from said internal output line and inverted inputs from said delay circuit, and having their outputs connected to the gates of their respective switch transistors.

Claim 40

The method of claim 30, further comprising the steps of: switching in a second transition from said HI to said LO output state when the input signal falls successively through said HI and LO threshold levels, inhibiting a reversion to said HI output state, for a delay period following said second transition that is no greater than the minimum period between a HI and a succeeding LO input state, unless said input signal rises above a boosted HI threshold level that is greater than said HI threshold level, enabling a reversion to said HI output state during said delay period following said second transition in response to said input signal rising above said boosted HI threshold level, and thereafter inhibiting a reversion to said HI output state unless said input signal rises above said HI threshold level.

Claim 41

The method of claim 31, wherein the delay periods following said first and second transitions are equal.

Claim 42

The method of claim 31, wherein said HI and LO threshold levels are restricted to a predetermined window of threshold levels over predetermined process, temperature and power supply ranges, and said boosted HI and boosted LO threshold levels are outside said window.

Claim 43

The method of claim 1, further comprising the step of enabling a reversion to said LO output state during said delay period in response to said input signal falling below said boosted LO threshold level.

Claim 44

The method of claim 2, further comprising the step of enabling a reversion to said HI output state during said delay period following said second transition in response to said input signal rising above said boosted HI threshold level.