US5113098A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Glitch remover circuit for transmission links
Assignee: Advanced Micro Devices Inc
•
Filing: 1991-03-29
•
Granted: 1992-05-12
•
Expires: 2011-03-29
Abstract
Abstract Glitch remover circuit for removing glitches and spikes from control signals received on a SCSI bus line that is coupled from a transmission line includes an input buffer circuit (12) and a filter circuit (14). The input buffer circuit is of a Schmitt trigger type having a transfer characteristic with hysteresis. The input buffer circuit (12) is responsive to control signals received at its input for removing noise spikes around the threshold point of its input on both the rising and falling edges of the control signals so as to provide a pulsed output voltage. The filter circuit (14) is responsive to the pulsed output voltage for generating a filtered pulsed signal at an output terminal only when the pulsed output voltage has a pulse width which is longer than a predetermined time. The filter circuit includes a delay means (28), a gating means (30) and inverter means (32).
Inventors
- 👤 Sassan Teymouri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:12
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
396 words
A glitch remover circuit for removing glitches and spikes from control signals received on a SCSI bus line that is coupled from a transmission line, comprising: input buffer means (12) being responsive to control signals received at its input fore removing noise spikes around the threshold point of its input on both the rising and falling edges of said control signals so as to provide a pulsed output voltage; said input buffer means including a Schmitt trigger type circuit having a transfer characteristic with hysteresis; said Schmitt trigger type circuit being formed of first through third N-channel MOS transistors (N1-N3), first through third P-channel MOS transistors (P1-P3), and an inverter gate (G1); said first N-channel transistor (N1) having its gates connected to the gate of said first P-channel transistor (P2) and its drain connected to the drain of said first P-channel transistor (P1), said first N-channel and P-channel transistors having their gates connected together and to receive said control signals and having their drains connected together and to the input of said inverter gate (G1); said second N-channel transistor (N2) having its drain connected to the source of said first N-channel transistor (N1), its gate connected to the gate of said first N-channel transistor (N1), and its source connected to a ground potential, said third N-channel transistor (N3) having its drain connected to a supply potential, its gate connected to the input of said inverter gate (G1), and its source connected to the drain of said second N-channel transistor (N2); said first P-channel transistor (P1) having its gate connected to the gate of said second P-channel transistor (P2) and its source connected to the drain of said second P-channel transistor (P2); said second P-channel transistor (P2) having its source connected to the supply potential, said third P-channel transistor (P3) having its source connected to the drain of said second P-channel transistor (P2), its gate connected to the input of said inverter gate (G1), and its drain connected to the ground potential, the output of said inverter gate (G1) providing the pulsed output voltage; filtering means (14) responsive to said pulsed output voltage for generating a filtered pulsed signal at an output terminal only when said pulsed output voltage has a pulse width which is longer than a predetermined time; and said filtering means being formed of delay means (28), gating means (30) and inverter means (32).
Claim 2
Dependent Claim
396 words
A glitch remover circuit for removing glitches and spikes from control signals received on a SCSI bus line that is coupled from a transmission line, comprising: input buffer means (12) being responsive to control signals received at its input fore removing noise spikes around the threshold point of its input on both the rising and falling edges of said control signals so as to provide a pulsed output voltage; said input buffer means including a Schmitt trigger type circuit having a transfer characteristic with hysteresis; said Schmitt trigger type circuit being formed of first through third N-channel MOS transistors (N1-N3), first through third P-channel MOS transistors (P1-P3), and an inverter gate (G1); said first N-channel transistor (N1) having its gates connected to the gate of said first P-channel transistor (P2) and its drain connected to the drain of said first P-channel transistor (P1), said first N-channel and P-channel transistors having their gates connected together and to receive said control signals and having their drains connected together and to the input of said inverter gate (G1); said second N-channel transistor (N2) having its drain connected to the source of said first N-channel transistor (N1), its gate connected to the gate of said first N-channel transistor (N1), and its source connected to a ground potential, said third N-channel transistor (N3) having its drain connected to a supply potential, its gate connected to the input of said inverter gate (G1), and its source connected to the drain of said second N-channel transistor (N2); said first P-channel transistor (P1) having its gate connected to the gate of said second P-channel transistor (P2) and its source connected to the drain of said second P-channel transistor (P2); said second P-channel transistor (P2) having its source connected to the supply potential, said third P-channel transistor (P3) having its source connected to the drain of said second P-channel transistor (P2), its gate connected to the input of said inverter gate (G1), and its drain connected to the ground potential, the output of said inverter gate (G1) providing the pulsed output voltage; filtering means (14) responsive to said pulsed output voltage for generating a filtered pulsed signal at an output terminal only when said pulsed output voltage has a pulse width which is longer than a predetermined time; and said filtering means being formed of delay means (28), gating means (30) and inverter means (32).
Claim 3
Dependent Claim
70 words
A glitch remover circuit as claimed in claim 1, wherein said gating means (30) is comprised of a NOR logic gate (G4) having a first input, a second input, and an output, wherein said delay means (30) is comprised of a series connection of a first CMOS inverter gate (G2) and a second CMOS inverter gate (G3), and wherein said inverter means (32) is comprised of an inverter gate (G5).
Claim 4
Dependent Claim
70 words
A glitch remover circuit as claimed in claim 2, wherein said NOR logic gate (G4) has its first input connected to receive said pulsed output voltage and has its second input connected to receive said pulsed output voltage via said first and second inverters (G2, G3), and its output connected to the input of said inverter gate (G5), the output of said inverter gate (G5) providing said filtered pulsed signal.
Claim 5
Dependent Claim
38 words
A glitch remover circuit as claimed in claim 3, wherein said pulsed output voltage is delayed from the input of said first inverter gate (G2) to the output of said second inverter gate (G3) by approximately 30 ns.
Claim 6
Dependent Claim
41 words
A glitch remover circuit as claimed in claim 4, wherein said first CMOS inverter gate (G2) is comprised of a P-channel MOS transistor and an N-channel MOS transistor whose width-to-length gate dimensions thereof are ratioed to provide a low trip point.
Claim 7
Dependent Claim
41 words
A glitch remover circuit as claimed in claim 5, wherein said second CMOS inverter gate (G3) is comprised of a P-channel MOS transistor and an N-channel MOS transistor whose width-to-length gate dimensions thereof are ratioed to provide a high trip point.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |