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US5341010A
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Semiconductor device including nonvolatile memories
Assignee: Rohm Co Ltd
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Filing: 1993-01-11
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Granted: 1994-08-23
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Expires: 2013-01-11
Abstract
Abstract The present invention can provide the memory circuit which has advantages in integration and the manufacturing expense and is easy to manufacture. The nonvolatile memory 21 comprises a P type well for which a N+ type source 4 and a N+ type drain 3 are provided. A surface of a space between the source 4 and the drain 3 comprises a first portion 10a and a second portion 10b. An insulating layer 6 for holding electrons spans the surface of the space. A memory gate electrode 5 is on the insulating layer 6 and spans the first portion 10a. A body 23 of high dielectric material is formed on the surface of the insulating layer 6 so that it connects to the memory gate electrode 5 through an insulating film 8 and spans the second portion 10b.
Inventors
- 👤 Noriyuki Shimoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
135 words
A semiconductor device including nonvolatile memories comprising: a substrate of semiconductor; a first region formed in the surface of the substrate; a second region formed in the surface of the substrate and defining a space between the first region and the second region, the surface of the space comprising a first portion and a second portion; an insulating layer for holding electrons spanning the first portion; a control electrode on the insulating layer for holding electrons and spanning the first portion, the control electrode having a side surface; a dielectric body which is formed of a high dielectric material and which spans the second portion adjacent to the side surface of the control electrode; and a first region electrode contacting the first region and the dielectric body, which is electrically isolated from the control electrode.
Claim 2
Dependent Claim
135 words
A semiconductor device including nonvolatile memories comprising: a substrate of semiconductor; a first region formed in the surface of the substrate; a second region formed in the surface of the substrate and defining a space between the first region and the second region, the surface of the space comprising a first portion and a second portion; an insulating layer for holding electrons spanning the first portion; a control electrode on the insulating layer for holding electrons and spanning the first portion, the control electrode having a side surface; a dielectric body which is formed of a high dielectric material and which spans the second portion adjacent to the side surface of the control electrode; and a first region electrode contacting the first region and the dielectric body, which is electrically isolated from the control electrode.
Claim 3
Dependent Claim
38 words
A semiconductor device including nonvolatile memories according to claim 1, wherein the insulating layer comprises a silicon dioxide layer, a silicon nitride layer on the silicon dioxide layer and a silicon dioxide layer on the silicon nitride layer.
Claim 4
Dependent Claim
29 words
A semiconductor device including nonvolatile memories according to claim 1, wherein the insulating layer comprises a silicon dioxide layer and a silicon nitride layer on the silicon dioxide layer.
Claim 5
Dependent Claim
42 words
A semiconductor device including nonvolatile memories according to claim 1, wherein the first region and the second region are made of semiconductor of P type conductivity and the first portion and the second portion are made of semiconductor of N type conductivity.
Claim 6
Dependent Claim
42 words
A semiconductor device including nonvolatile memories according to claim 1, wherein the first region and the second region are made of semiconductor of N type conductivity and the first portion and the second portion are made of semiconductor of P type conductivity.
Claim 7
Dependent Claim
32 words
A semiconductor device including nonvolatile memories according to claim 1, wherein the first region is a source, the second region is a drain and the control electrode is a memory gate electrode.
Claim 8
Dependent Claim
26 words
A semiconductor device including nonvolatile memories according to claim 1, further comprising: an insulator layer between the second portion and the body of high dielectric material.
Claim 9
Dependent Claim
18 words
A semiconductor device including nonvolatile memories according to claim 7, wherein the insulating layer is to hold electrons.
Claim 10
Dependent Claim
133 words
A method for operating memories of claim 6 comprising: arraying the memories in rows and columns; connecting drain lines to the drains of the memories arrayed in each of said rows; connecting gate lines to the memory gate electrodes of the memories arrayed in each of said columns; connecting a source line to the sources of all the memories arrayed in said rows and columns; and reading data from a selected memory by determining whether a current flows through a drain line connected to the drain of the selected memory when a sense voltage is applied to a gate line connected to the memory gate electrode of the selected memory as well as applying a reading voltage to the source line wherein said reading voltage renders said second portion of said substrate conductive.
Claim 11
Dependent Claim
36 words
A semiconductor device, according to claim 1, wherein a height of said dielectric body is substantially the same as that of said control electrode, and a width of the dielectric body is smaller than said height.
Claim 12
Dependent Claim
29 words
A semiconductor device, according to claim 1, wherein said dielectric body is formed by anisotropic etching a high dielectric material layer provided on an entire surface of said substrate.
Claim 13
Dependent Claim
18 words
A semiconductor device, according to claim 1, wherein the high dielectric material is Ta 2 O 5 .
Claim 14
Dependent Claim
14 words
A semiconductor device, according to claim 1, wherein the high dielectric material is PZT.
Claim 15
Dependent Claim
16 words
A semiconductor device, according to claim 1, wherein the high dielectric material is SrTiO 3 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |