Patent US5339408A successfully refreshed from Google Patents.
US5339408A
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US
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Method and apparatus for reducing checking costs in fault tolerant processors
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-12-30
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Granted: 1994-08-16
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Expires: 2012-12-30
Abstract
Abstract According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.
Inventors
- 👤 William Bruckert
- 👤 Thomas D. Bissett
- 👤 Glenn Dearth
- 👤 Paul Paternoster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:11
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1633; G06F11/1641; G06F11/1645; G06F11/1658; G06F11/1675; G06F11/1679; G06F11/1683; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; G06F11/006; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G06F11/1604; G06F11/1654; G06F11/20; G06F11/22; G06F11/2205; H03D; H03D13/00; H03D13/003; H03L7/089
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
77 words
An apparatus comprising: a central processing unit comprising: first and second processors to process an identical instruction stream; a data bus coupled to said first and second processors; means for providing said first processor to furnish data to said data bus and to receive data from said data bus in response to said identical instruction stream; and means for providing said second processor to receive data from said data bus in response to said identical instruction stream.
Claim 2
Independent Claim
77 words
An apparatus comprising: a central processing unit comprising: first and second processors to process an identical instruction stream; a data bus coupled to said first and second processors; means for providing said first processor to furnish data to said data bus and to receive data from said data bus in response to said identical instruction stream; and means for providing said second processor to receive data from said data bus in response to said identical instruction stream.
Claim 3
Dependent Claim
126 words
The apparatus of claim 1 further comprising: a first system bus comprising an address bus, a control bus, an error code bus and said data bus, coupled to said first processor, to provide data to a cache and a memory; a second abbreviated system bus comprising an address bus, a control bus, and an error code bus, coupled to said second processor to provide data to said cache and said memory; error checking means for comparing said corresponding busses of said first system bus to said second abbreviated system bus to detect inconsistencies; and error correction means for comparing said an error code of said data bus with said error code bus of said first system bus to check and correct errors in said data bus.
Claim 4
Dependent Claim
83 words
The apparatus of claim 1 further comprising: a cache comprising: a cache memory coupled to said data bus to store data provided by said first processor; first and second tag storage means for storing addresses provided by and received by said first and second processors respectively in response to said identical instruction stream; and first and second error code storage means for storing error codes provided by and received by said first and second processors respectively in response to said identical instruction stream.
Claim 5
Dependent Claim
106 words
The apparatus of claim 1 further comprising: a main memory further comprising: first and second memory control means for storing a first and second address and a control data provided by said first and second processors respectively in response to said identical instruction stream; first error storage means for storing a first error code provided by said first in response to said identical instruction stream; data storage means for storing data provided from said first processor on said data bus; and error checking means for comparing said first and second address data, said first and second control data, and said first and second error code data.
Claim 6
Dependent Claim
33 words
The apparatus of claim 4, wherein said error checking means compares said first and second data to detect an inconsistency between address, control and error data provided by the first and second processors.
Claim 7
Dependent Claim
35 words
The apparatus of claim 4 further comprising error detection means for generating an error code from data stored in said data storage means and for comparing said generated error code to said first error code.
Claim 8
Dependent Claim
21 words
The apparatus of claim 1, further comprising a plurality of said computer processing systems operating on said identical instruction stream simultaneously.
Claim 9
Independent Claim
140 words
An apparatus comprising: a central processing unit comprising: first and second processors to process an identical instruction stream; a first system bus comprising a data bus coupled to said first and second processors with said first processor providing data to said data bus and receiving data from said data bus in response to said identical instruction stream and said second processor receiving data from said data bus and checking said data on said data bus for accuracy, said first system bus further comprising: a first address bus, a first error bus and a first control bus coupled to said first processor; and with said apparatus further comprising a second abbreviated system bus coupled to said second processor comprising a second address bus, a second error bus and a second control bus, and said data bus of said first system bus.
Claim 10
Independent Claim
140 words
An apparatus comprising: a central processing unit comprising: first and second processors to process an identical instruction stream; a first system bus comprising a data bus coupled to said first and second processors with said first processor providing data to said data bus and receiving data from said data bus in response to said identical instruction stream and said second processor receiving data from said data bus and checking said data on said data bus for accuracy, said first system bus further comprising: a first address bus, a first error bus and a first control bus coupled to said first processor; and with said apparatus further comprising a second abbreviated system bus coupled to said second processor comprising a second address bus, a second error bus and a second control bus, and said data bus of said first system bus.
Claim 11
Dependent Claim
69 words
The apparatus of claim 8 further comprising: a cache comprising: a cache memory coupled to said data bus, said first address bus and said first control bus; first and second tag storage means for storing data on said first and second address bus and said first and second control bus respectively; and first and second error storage means for storing data on said first and second error busses respectively.
Claim 12
Dependent Claim
129 words
The apparatus of claim 8 further comprising: a main memory further comprising: first and second memory control means for storing a first data on said first and second address and said first and second control bus respectively; first and second error storage means for storing data on said first and second error code busses respectively; data storage means for storing data on said data bus; error checking means for comparing said address and control data from said first and second tag storage means, and for comparing data from said first and second error storage means; and error detection means for generating an error code from data stored in said data storage means and for comparing said generated error code to said data stored in said first error storage means.
Claim 13
Dependent Claim
21 words
The apparatus of claim 8, further comprising a plurality of said computer processing systems operating on said identical instruction stream simultaneously.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |