Asynchronous TMR processing system

Claim 2

An asynchronous triple modular redundancy processing system with local arbitration, comprising: N processor elements, N arbiter elements associated respectively with each of said processor elements, a memory uniquely associated with each processor element, a bidirectional control bus between each arbiter and its associated processor, and a unidirectional control bus between each processor arbiter and the other processors of the system, means for providing each processor with knowledge of which processor of the system is a requestor, means for providing to each processor which requester of other elements is competing for service within said system, and a plurality of voters for providing service arbitration votes with voting for output transmission and without voting for inputs.

Claim 3

The system of claim 1 wherein each processor is provided with means for permitting each processor element to operate on its own clock time.

Claim 4

The system of claim 1 where the voters provide service arbitration votes which function as a N to 1 combiner with voting for output transmission and a 1 N splitter without voting for inputs.

Claim 5

The system of claim 1 wherein "N" is three.

Claim 6

The system of claim 3 wherein "N" is three.

Claim 7

An asynchronous redundant processing system with local arbitration comprising: N processor elements each having its own clock time and running the same program; N global memories each coupled to a respective processor element; N arbitrators, each arbitrator coupled to one associated processor element by a bidirectional control bus and each arbitrator connected to the other N-1 processor elements by a unidirectional control bus for receiving signals from said other N-1 processor elements, said arbitrators requiring said processor elements fetch operations from global memories to occur simultaneously to provide synchronism among said processor elements; an input output interface; and a voter for providing bidirectional data transmission to and from said N processor elements and said input output interface, said voter functioning as an N to one combiner with voting in connection with data streams from said N processor elements for output transmissions to said input output interface, said voter functioning as a one to N splitter without voting for inputs from said input output interface to said N processor elements.

Claim 8

An asynchronous redundant processing system with local arbitration comprising: N processor elements each having its own clock time and running the same program; N global memories each coupled to a respective processor element; N arbitrators, each arbitrator coupled to one associated processor element by a bidirectional control bus and each arbitrator connected to the other N-1 processor elements by a unidirectional control bus for receiving signals from said other N-1 processor elements, said arbitrators requiring said processor elements fetch operations from global memories to occur simultaneously to provide synchronism among said processor elements; an input output interface; and a voter for providing bidirectional data transmission to and from said N processor elements and said input output interface, said voter functioning as an N to one combiner with voting in connection with data streams from said N processor elements for output transmissions to said input output interface, said voter functioning as a one to N splitter without voting for inputs from said input output interface to said N processor elements.

Claim 9

The system of claim 6, wherein "N" is three.