US5117442A
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Methods and circuits for synchronizing signals in a modular redundant fault tolerant computer system
Assignee: National Semiconductor Corp
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Filing: 1988-12-14
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Granted: 1992-05-26
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Expires: 2008-12-14
Abstract
Abstract A fault tolerant circuit and method of synchronizing multiple asynchronous input signals, such as reset signals, in a modular redundant fault-tolerant computer system in which clock signals or respective slices have a bounded skew with respect to one another. The input signal and clock signal for each slice of the system are used to produce an initial synchronization signal in each slice of a first layer of the circuit. Each initial synchronization signal is used with an inverted version of each of the slice clock signals to produce, in each slice of a second layer of the circuit, a set of local synchronization signals for each slice. The local synchronization signals for each slice are passed to a majority-voter which produces a voted output signal for the slice. The voted output signal and the clock signal for each slice are then used to produce a finally synchronized output signal for that slice. The output signals for the multiple slices are synchronized to the respectively associated slice clock signals, and to one another within the bounded skew of the slice clock signals.
Inventors
- 👤 Christopher M. Hall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:12
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F11/1675; G06F11/1679
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
239 words
Apparatus for synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal, and said clock signals have a defined period and are skewed relative to one another, said apparatus comprising: first means responsive to said input signals and said clock signals for producing an initial synchronization signal corresponding to each said input signal and which is synchronized with the beginning of a period of the clock signal associated with said input signal; second means responsive to said initial synchronization signals and said clock signals for producing a respective set of local synchronization signals for each said clock signal, each said set of local synchronization signals corresponding to said initial synchronization signals and being synchronized with the midpoint of a period of the respective clock signal; third means responsive to said local synchronization signals for comparing each said set of local synchronization signals and for producing a comparison output signal for each said comparison; and fourth means responsive to said comparison output signals and said clock signals for producing a final synchronization signal for each said comparison output signal, each said final synchronization signal being synchronized with the beginning of a clock period of the same clock signal with which the set of local synchronization signals used to produce the comparison output signal was synchronized, such that said final synchronization signals are mutually synchronized within the limits of the skew between said clock signals.
Claim 2
Dependent Claim
239 words
Apparatus for synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal, and said clock signals have a defined period and are skewed relative to one another, said apparatus comprising: first means responsive to said input signals and said clock signals for producing an initial synchronization signal corresponding to each said input signal and which is synchronized with the beginning of a period of the clock signal associated with said input signal; second means responsive to said initial synchronization signals and said clock signals for producing a respective set of local synchronization signals for each said clock signal, each said set of local synchronization signals corresponding to said initial synchronization signals and being synchronized with the midpoint of a period of the respective clock signal; third means responsive to said local synchronization signals for comparing each said set of local synchronization signals and for producing a comparison output signal for each said comparison; and fourth means responsive to said comparison output signals and said clock signals for producing a final synchronization signal for each said comparison output signal, each said final synchronization signal being synchronized with the beginning of a clock period of the same clock signal with which the set of local synchronization signals used to produce the comparison output signal was synchronized, such that said final synchronization signals are mutually synchronized within the limits of the skew between said clock signals.
Claim 3
Dependent Claim
42 words
The apparatus of claim 1, wherein the sum of (a) the skew between said clock signals, and (b) the output delay of said first means, and (c) the input setup of said second means, equals less than one-half of said defined period.
Claim 4
Dependent Claim
42 words
The apparatus of claim 1, wherein said first means comprises a set of latches, each said latch coupled to receive a respective one of said input signals and the associated said clock signal and to produce one of said initial synchronization signals.
Claim 5
Dependent Claim
41 words
The apparatus of claim 1, wherein said second means comprises a set of latches, each said latch coupled to receive one of said initial synchronization signals and one of said clock signals and to produce one of said local synchronization signals.
Claim 6
Dependent Claim
60 words
The apparatus of claim 1, wherein at least three of said digital output signals are provided as inputs and said third means comprises a set of voting circuits, each said voting circuit coupled to receive one said set of said local synchronization signals, whereby said comparison output signal represents the logical majority vote of said set of local synchronization signals.
Claim 7
Dependent Claim
44 words
The apparatus of claim 1, wherein said fourth means comprises a set of latches, each said latch coupled to receive a respective one of said comparison output signals and an associated one of said clock signals and to produce one of said final signals.
Claim 8
Dependent Claim
20 words
The apparatus of claim 1, further comprising means responsive to an override signal for overriding synchronization of said input signals.
Claim 9
Dependent Claim
32 words
The apparatus of claim 7, wherein said overriding means comprises means for holding in a cleared state the outputs of said third means and bypassing said input signals to said fourth means.
Claim 10
Dependent Claim
45 words
The apparatus of claim 1, wherein said second means is responsive to an override signal for producing at least one set of local synchronization signals which, when applied to said third means, results in a comparison output signal corresponding to one of said input signals.
Claim 11
Independent Claim
196 words
A method of synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal, and said clock signals have a defined period and are skewed relative to one another, comprising the steps of: a. producing an initial synchronization signal corresponding to each said input signal and which is synchronized with the beginning of a period of the clock signal associated with said input signal; b. producing a respective set of local synchronization signals for each said clock signal, each said set of local synchronization signal corresponding to said initial synchronization signals and being synchronized with the midpoint of a period of the respective clock signal; c. comparing each said set of local synchronization signals and producing a comparison output signal for each said comparison; and d. producing a final synchronization signal for each said comparison output signal, each said final synchronization signal being synchronized with the beginning of a clock period of the same clock signal with which the set of local synchronization signals used to produce the comparison output signal was synchronized, whereby said final synchronization signals are mutually synchronized within the limits of the skew between said clock signals.
Claim 12
Independent Claim
196 words
A method of synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal, and said clock signals have a defined period and are skewed relative to one another, comprising the steps of: a. producing an initial synchronization signal corresponding to each said input signal and which is synchronized with the beginning of a period of the clock signal associated with said input signal; b. producing a respective set of local synchronization signals for each said clock signal, each said set of local synchronization signal corresponding to said initial synchronization signals and being synchronized with the midpoint of a period of the respective clock signal; c. comparing each said set of local synchronization signals and producing a comparison output signal for each said comparison; and d. producing a final synchronization signal for each said comparison output signal, each said final synchronization signal being synchronized with the beginning of a clock period of the same clock signal with which the set of local synchronization signals used to produce the comparison output signal was synchronized, whereby said final synchronization signals are mutually synchronized within the limits of the skew between said clock signals.
Claim 13
Dependent Claim
33 words
The method of claim 10, wherein step c. comprises logically comparing the local synchronization signals of said set with one another such that said comparison output signal comprises a logical majority voted output.
Claim 14
Dependent Claim
240 words
Apparatus for synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal and said clock signals have a defined period and are skewed relative to one another, said apparatus comprising for each said input signal: first means responsive to said input signal and to the clock signal associated with said input signal for producing an initial synchronization signal which corresponds to said input signal and which is synchronized to the beginning of a period of said associated clock signal; second means responsive to said initial synchronization signal, to the clock signal associated with said input signal, and to the initial synchronization signals produced in response to the other of said input signals, for producing a set of local synchronization signals which correspond to said initial synchronization signals and which are synchronized to the midpoint of a period of the clock signal associated with said input signal; third means for comparing said set of local synchronization signals and producing a comparison output signal; and fourth means responsive to said comparison output signal and to the clock signal associated with said input signal for producing a final synchronization signal which corresponds to said comparison output signal and which is synchronized to the beginnning of a period of the clock signal associated with said input signal, such that said final synchronization signals are synchronized to one another within the limits of the skew between said clock signals.
Claim 15
Dependent Claim
240 words
Apparatus for synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal and said clock signals have a defined period and are skewed relative to one another, said apparatus comprising for each said input signal: first means responsive to said input signal and to the clock signal associated with said input signal for producing an initial synchronization signal which corresponds to said input signal and which is synchronized to the beginning of a period of said associated clock signal; second means responsive to said initial synchronization signal, to the clock signal associated with said input signal, and to the initial synchronization signals produced in response to the other of said input signals, for producing a set of local synchronization signals which correspond to said initial synchronization signals and which are synchronized to the midpoint of a period of the clock signal associated with said input signal; third means for comparing said set of local synchronization signals and producing a comparison output signal; and fourth means responsive to said comparison output signal and to the clock signal associated with said input signal for producing a final synchronization signal which corresponds to said comparison output signal and which is synchronized to the beginnning of a period of the clock signal associated with said input signal, such that said final synchronization signals are synchronized to one another within the limits of the skew between said clock signals.
Claim 16
Dependent Claim
42 words
The apparatus of claim 12, wherein the sum of (a) the skew between said clock signals, and (b) the output delay of said first means, and (c) the input setup of said second means, equals less that one-half of said defined period.
Claim 17
Dependent Claim
36 words
The apparatus of claim 13, wherein said first means comprises a latch coupled to receive said input signal and the clock signal associated with said input signal and to produce one of said initial synchronization signals.
Claim 18
Dependent Claim
44 words
The apparatus of claim 14, wherein said second means comprises a set of latches, each said latch coupled to receive one of said initial synchronization signals and the clock signal associated with said input signal and to produce one of said local synchronization signals.
Claim 19
Dependent Claim
62 words
The apparatus of claim 15, wherein at least three of said digital input signals are provided as inputs and said third mens comprises a majority voting circuit coupled to receive one said set of said local synchronization signals and to produce said comparison output signal, whereby said comparison output signal represents the logical majority vote of said set of local synchronization signals.
Claim 20
Dependent Claim
35 words
The apparatus of claim 16, wherein said fourth means comprises a latch coupled to receive said comparison output signal and said clock signal associated with said input signal and to produce said final synchronization signals.
Claim 21
Dependent Claim
20 words
The apparatus of claim 17, further comprising means responsive to an override signal for overriding synchronization of said input signals.
Claim 22
Dependent Claim
32 words
The apparatus of claim 18, wherein said overriding means comprises means for holding in a cleared state the outputs of said third means and bypassing said input signals to said fourth means.
Claim 23
Dependent Claim
47 words
The apparatus of claim 12, wherein said second means is responsive to an override signal for producing said set of local synchronization signals such that, when said set of local synchronization is applied to said third means, said comparison output signal corresponds one of said input signals.
Claim 24
Independent Claim
162 words
A method of synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal and said clock signals have a defined period and are skewed relative to one another, comprising for each said input signal the steps of: producing an initial synchronization signal which corresponds to said input signal and which is synchronized to the beginning of a period of said associated clock signal; producing, for each said clock signal, a set of local synchronization signals which correspond to said initial synchronization signals and which are synchronized to the midpoint of said clock signal; comparing said set of local synchronization signals and producing a comparison output signal; and producing a final synchronization signal which corresponds to said comparison output signal and which is synchronized to the beginning of a period of the clock signal associated with said input signal, whereby said final synchronization signals are mutually synchronized within the limits of the skew between said clock signals.
Claim 25
Independent Claim
162 words
A method of synchronizing multiple digital input signals, wherein each said input signal is associated with a clock signal and said clock signals have a defined period and are skewed relative to one another, comprising for each said input signal the steps of: producing an initial synchronization signal which corresponds to said input signal and which is synchronized to the beginning of a period of said associated clock signal; producing, for each said clock signal, a set of local synchronization signals which correspond to said initial synchronization signals and which are synchronized to the midpoint of said clock signal; comparing said set of local synchronization signals and producing a comparison output signal; and producing a final synchronization signal which corresponds to said comparison output signal and which is synchronized to the beginning of a period of the clock signal associated with said input signal, whereby said final synchronization signals are mutually synchronized within the limits of the skew between said clock signals.
Claim 26
Dependent Claim
108 words
Apparatus for synchronizing multiple digital signals associated with respective clock signals, comprising: a. means responsive to said digital signals and to said clock signals for producing a set of initial synchronization signals; b. means responsive to said clock signals and said initial synchronization signals for producing a set of local synchronization signals for each said clock signal; c. means responsive to said local synchronization signals for producing a set of comparison signals; d. means responsive to said clock signals and said comparison signals for producing a set of final synchronization signals, such that said final synchronization signals are mutually synchronized and synchronized to their respective associated clock signals.
Claim 27
Dependent Claim
108 words
Apparatus for synchronizing multiple digital signals associated with respective clock signals, comprising: a. means responsive to said digital signals and to said clock signals for producing a set of initial synchronization signals; b. means responsive to said clock signals and said initial synchronization signals for producing a set of local synchronization signals for each said clock signal; c. means responsive to said local synchronization signals for producing a set of comparison signals; d. means responsive to said clock signals and said comparison signals for producing a set of final synchronization signals, such that said final synchronization signals are mutually synchronized and synchronized to their respective associated clock signals.
Claim 28
Independent Claim
114 words
A method of synchronizing multiple digital signals associated with respective clock signals, comprising the steps of: a. producing a set of initial synchronization signals in response to said digital signals and to said clock signals; b. producing multiple sets of local synchronization signals in response to said clock signals and said initial synchronization signals, each said set of local synchronization signals corresponding to one of said clock signals; c. producing a set of comparison signals in response to said local synchronization signals; d. producing a set of final synchronization signals in response to said clock signals and said comparison signals, said final synchronization signals being mutually synchronized and synchronized to respective associated clock signals.
Claim 29
Independent Claim
114 words
A method of synchronizing multiple digital signals associated with respective clock signals, comprising the steps of: a. producing a set of initial synchronization signals in response to said digital signals and to said clock signals; b. producing multiple sets of local synchronization signals in response to said clock signals and said initial synchronization signals, each said set of local synchronization signals corresponding to one of said clock signals; c. producing a set of comparison signals in response to said local synchronization signals; d. producing a set of final synchronization signals in response to said clock signals and said comparison signals, said final synchronization signals being mutually synchronized and synchronized to respective associated clock signals.
References Cited (Backward Citations)
US4232387A
Cited
US4302831A
Cited
US4348762A
Cited
US4330826A
Cited
US4375683A
Cited
US4498176A
Cited
US4583224A
Cited
US4644498A
Cited
US4589066A
Cited
US4696019A
Cited
US4692932A
Cited
US4700346A
Cited
US4683570A
Cited
US4782499A
Cited
US4833695A
Cited
US4860322A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |