US5339344A
Expired / Lapsed
US
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Counter device and method of operating the same
Assignee: Mitsubishi Electric Corp
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Filing: 1993-08-05
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Granted: 1994-08-16
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Expires: 2013-08-05
Abstract
Abstract A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the Jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.
Inventors
- 👤 Masatoshi Kimura
- 👤 Minobu Yazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:49
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/665; H03K21/00; H03K21/38
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
147 words
A semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, comprising: counting means for counting a clock signal to generate a row address indicating a row in said memory cell array; storage means for storing a defective row address specifying a defective row having a defective memory cell connected thereto in said memory cell array; comparing means for comparing a count of said count means and said defective row address; adjusting means coupled to receive an output of said comparing means and operable in response thereto, for skipping a count of said counting means to the very next count upon coincidence of the count of said counting means and said defective row address; and decoder means coupled to receive the generated row address from said counting means for selecting a corresponding row in said memory cell array.
Claim 2
Dependent Claim
147 words
A semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, comprising: counting means for counting a clock signal to generate a row address indicating a row in said memory cell array; storage means for storing a defective row address specifying a defective row having a defective memory cell connected thereto in said memory cell array; comparing means for comparing a count of said count means and said defective row address; adjusting means coupled to receive an output of said comparing means and operable in response thereto, for skipping a count of said counting means to the very next count upon coincidence of the count of said counting means and said defective row address; and decoder means coupled to receive the generated row address from said counting means for selecting a corresponding row in said memory cell array.
Claim 3
Dependent Claim
139 words
A semiconductor memory device according to claim 1, further comprising: second counting means for counting a second clock signal to generate a column address indicating a column in said memory cell array; second storage means for storing a defective column address indicating a defective column having a defective memory cell connected thereto; comparing means for comparing a count of said counting means and the defective column address; adjusting means coupled to receive an output of said comparing means and operable in response thereto, for skipping a count of said second counting means to the very next count upon coincidence of the count of said second counting means and said defective column address; and second decoder means coupled to receive an output of said second counting means and operable in response thereto, for selecting a corresponding column in said array.
Claim 4
Dependent Claim
141 words
A semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, comprising: counting means for counting a clock signal to provide a count as its output; decoder means coupled to receive an output of said counting means and operable in response thereto, for selecting a corresponding column in said memory cell array; storage element for storing a defective column address specifying a defective column having a defective memory cell connected thereto in said memory cell array; comparing means for comparing a count of said counting means and said defective column address; and modifying means coupled to receive an output of said comparing means and operable in response thereto, for modifying a count of said counting means by one upon coincidence of the count of said counting means and said defective column address.
Claim 5
Dependent Claim
141 words
A semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, comprising: counting means for counting a clock signal to provide a count as its output; decoder means coupled to receive an output of said counting means and operable in response thereto, for selecting a corresponding column in said memory cell array; storage element for storing a defective column address specifying a defective column having a defective memory cell connected thereto in said memory cell array; comparing means for comparing a count of said counting means and said defective column address; and modifying means coupled to receive an output of said comparing means and operable in response thereto, for modifying a count of said counting means by one upon coincidence of the count of said counting means and said defective column address.
Claim 6
Independent Claim
120 words
A method for operating a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, and a storage circuit for storing a defective row address specifying a defective row having a defective memory cell connected thereto in said memory cell array, comprising the steps of: counting a clock signal for providing a count as a row address specifying a row in said memory cell array; comparing the count with the defective row address; skipping the count to the very next count upon coincidence of the count and the defective row address, to generate a row address; and decoding a row address to select a corresponding row in said memory cell array.
Claim 7
Independent Claim
120 words
A method for operating a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, and a storage circuit for storing a defective row address specifying a defective row having a defective memory cell connected thereto in said memory cell array, comprising the steps of: counting a clock signal for providing a count as a row address specifying a row in said memory cell array; comparing the count with the defective row address; skipping the count to the very next count upon coincidence of the count and the defective row address, to generate a row address; and decoding a row address to select a corresponding row in said memory cell array.
Claim 8
Independent Claim
117 words
A method of operating a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, and storage circuit for storing a defective column address specifying a defective column having a defective memory cell connected thereto, comprising the steps of: counting a clock signal to provide a count as a column address specifying a column in said memory cell array; comparing the count with said defective column address; modifying the count by one count upon coincidence of the count and said defective column address; and decoding a column address to select a corresponding column in said memory cell array, to connect the corresponding column to an internal data bus.
Claim 9
Independent Claim
117 words
A method of operating a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, and storage circuit for storing a defective column address specifying a defective column having a defective memory cell connected thereto, comprising the steps of: counting a clock signal to provide a count as a column address specifying a column in said memory cell array; comparing the count with said defective column address; modifying the count by one count upon coincidence of the count and said defective column address; and decoding a column address to select a corresponding column in said memory cell array, to connect the corresponding column to an internal data bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |