Patent US5337338A successfully refreshed from Google Patents.
US5337338A
Expired / Lapsed
US
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Pulse density modulation circuit (parallel to serial) comparing in a nonsequential bit order
Assignee: Qualcomm Inc
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Filing: 1993-02-01
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Granted: 1994-08-09
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Expires: 2013-02-01
Abstract
Abstract A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input. The circuit may further filter the comparator output to provide a resultant analog output signal.
Inventors
- 👤 Todd Sutton
- 👤 Sherman Gregory
- 👤 Joan T. Waltman
- 👤 Katherine W. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:42
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/04
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
92 words
A pulse density modulation circuit comprising: counter means for generating a series of incremental value count signals, each count signal having a most significant bit through a least significant bit; and comparator means for receiving a reference signal having a most significant bit through least significant bit, comparing the reference signal with the series of count signals wherein the reference signal most significant bit through least significant bit is compared in a non-sequential bit order of the count signal most significant bit through least significant bit, and providing a single bit signal.
Claim 2
Dependent Claim
92 words
A pulse density modulation circuit comprising: counter means for generating a series of incremental value count signals, each count signal having a most significant bit through a least significant bit; and comparator means for receiving a reference signal having a most significant bit through least significant bit, comparing the reference signal with the series of count signals wherein the reference signal most significant bit through least significant bit is compared in a non-sequential bit order of the count signal most significant bit through least significant bit, and providing a single bit signal.
Claim 3
Dependent Claim
40 words
The circuit of claim 1 wherein the non-sequential bit order is a bit reversed order wherein the reference signal most significant bit through least significant bit is compared respectively with the count signal least significant bit through most significant bit.
Claim 4
Dependent Claim
15 words
The circuit of claim 1 further comprising filter means for filtering the single bit signal.
Claim 5
Dependent Claim
15 words
The circuit of claim 2 further comprising filter means for filtering the single bit signal.
Claim 6
Dependent Claim
96 words
A pulse density modulation circuit comprising: a counter having a clock input for receiving a clock signal and a most significant bit output through a least significant bit output; and a comparator having a first set of most significant bit through least significant bit inputs for respectively receiving a most significant bit through a least significant bit of an input reference signal and a second set of most significant bit through least significant bit inputs connected to the counter most significant bit output through least significant bit output in a non-sequential bit order, and an output.
Claim 7
Dependent Claim
96 words
A pulse density modulation circuit comprising: a counter having a clock input for receiving a clock signal and a most significant bit output through a least significant bit output; and a comparator having a first set of most significant bit through least significant bit inputs for respectively receiving a most significant bit through a least significant bit of an input reference signal and a second set of most significant bit through least significant bit inputs connected to the counter most significant bit output through least significant bit output in a non-sequential bit order, and an output.
Claim 8
Dependent Claim
49 words
The circuit of claim 5 wherein the non-sequential bit order is a bit reversed order wherein the counter most significant bit output through least significant bit output are respectively connected to the least significant bit input through the most significant bit input of the comparator second set of inputs.
Claim 9
Dependent Claim
21 words
The circuit of claim 5 further comprising a low-pass filter having an input connected to the comparator output and an output.
Claim 10
Dependent Claim
21 words
The circuit of claim 6 further comprising a low-pass filter having an input connected to the comparator output and an output.
Claim 11
Dependent Claim
41 words
A multibit to single bit signal converter comprising: means for providing a series of non-sequential values at a predetermined rate; and means for comparing a multibit input value with the series of non-sequential values to provide a resultant single bit signal.
Claim 12
Dependent Claim
41 words
A multibit to single bit signal converter comprising: means for providing a series of non-sequential values at a predetermined rate; and means for comparing a multibit input value with the series of non-sequential values to provide a resultant single bit signal.
Claim 13
Dependent Claim
22 words
The converter of claim 9 further comprising filter means for filtering the resultant single bit signal to provide a resultant analog signal.
Claim 14
Independent Claim
91 words
A method for creating pulse density modulated signal comprising the steps of: providing a series of incremental value count signals, each count signal having a most significant bit through a least significant bit; receiving a reference signal having most significant bit through least significant bit; comparing the reference signal with the series of count signals wherein the reference signal most significant bit through least significant bit is compared in a non-sequential bit order of each count signal most significant bit through least significant bit; and providing a corresponding single bit signal.
Claim 15
Independent Claim
91 words
A method for creating pulse density modulated signal comprising the steps of: providing a series of incremental value count signals, each count signal having a most significant bit through a least significant bit; receiving a reference signal having most significant bit through least significant bit; comparing the reference signal with the series of count signals wherein the reference signal most significant bit through least significant bit is compared in a non-sequential bit order of each count signal most significant bit through least significant bit; and providing a corresponding single bit signal.
Claim 16
Dependent Claim
40 words
The method of claim 11 wherein the non-sequential bit order is a bit reversed order wherein the reference signal most significant bit through least significant bit is compared respectively with the count signal least significant bit through most significant bit.
Claim 17
Dependent Claim
15 words
The method of claim 11 further comprising the step of filtering the single bit signal.
Claim 18
Dependent Claim
15 words
The circuit of claim 12 further comprising the step of filtering the single bit signal.
Claim 19
Independent Claim
43 words
A method of multibit to single bit signal conversion comprising the steps of: providing a series of non-sequential values at a predetermined rate; and comparing a multibit reference value with the series of non-sequential values to provide a corresponding single bit output signal.
Claim 20
Independent Claim
43 words
A method of multibit to single bit signal conversion comprising the steps of: providing a series of non-sequential values at a predetermined rate; and comparing a multibit reference value with the series of non-sequential values to provide a corresponding single bit output signal.
Claim 21
Dependent Claim
17 words
The method of claim 15 further comprising the step of filtering said corresponding single bit output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |