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US5336937A
Expired / Lapsed
US
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Programmable analog synapse and neural networks incorporating same
Assignee: State University of New York (System)
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Filing: 1992-08-28
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Granted: 1994-08-09
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Expires: 2012-08-28
Abstract
Abstract An analog synapse circuit for an artificial neural network requiring less circuitry and interconnections than prior synapses, while affording better weight programming means uses two complementary floating-gate MOSFETs with tunneling injection in an inverter configuration, with each MOSFET storing a weight value. This weight value is set by storing a charge injected by Fowler-Nordheim tunneling, or other tunneling means, into the floating-gate, which shifts the threshold voltage of the device. A programming line applies a current pulse to the MOSFET floating gate to write or erase this stored charge, thereby adjusting the weight of the MOSFET. The two MOSFETs are connected with the gate electrodes connected together and the drain electrodes connected together to provide a common gate and common drain between the two MOSFETs. An input line is connected to the common gate, and an output line is connected to the common drain. The source electrodes of each MOSFET are connected to reference voltages. The synapse circuit may be used in either a feedforword or feedback network, and may be expanded from two to four quadrant operation. The synapse provides a single output current line which represents a function of the input voltage and the stored weights. A plurality of such synapses may be configured in a network, wherein the output lines of each synapse are connected at a current summing node at the input of a neuron. An active load in the input of the neuron allows for both excitatory and inhibitory output current from the synapse circuit.
Inventors
- 👤 Ramalingam Sridhar
- 👤 Seokjin Kim
- 👤 Yong-Chul Shin
- 👤 Naidu C. R. Bogineni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:49
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063; G06N3/065
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
135 words
In an artificial neural-network composed of a plurality of analog synapses having programmable synaptic weights and at least one neuron, where said analog synapses each have a signal input line and an output line, said output line being connected to said neuron, to provide an output which is a function of the input signal on said input line and the synaptic weights presented by said synapses, characterized in that each of said plurality of synapses comprises two complementary floating gate MOSFETs in an inverter structure having an output connected to said output line, the gates of said MOSFETs being connected to said input line, each said MOSFET having separate means for setting a weight value therein, and means for transmitting a programming pulse to said MOSFETs floating gate for programming each weight of said MOSFETs.
Claim 2
Dependent Claim
135 words
In an artificial neural-network composed of a plurality of analog synapses having programmable synaptic weights and at least one neuron, where said analog synapses each have a signal input line and an output line, said output line being connected to said neuron, to provide an output which is a function of the input signal on said input line and the synaptic weights presented by said synapses, characterized in that each of said plurality of synapses comprises two complementary floating gate MOSFETs in an inverter structure having an output connected to said output line, the gates of said MOSFETs being connected to said input line, each said MOSFET having separate means for setting a weight value therein, and means for transmitting a programming pulse to said MOSFETs floating gate for programming each weight of said MOSFETs.
Claim 3
Dependent Claim
24 words
The invention according to claim 1 where one of said two MOSFETs is of P-type and the other of said MOSFETs is of N-type.
Claim 4
Dependent Claim
46 words
The invention according to claim 1 wherein said input signal line is connected in common to the gates of said MOSFETs, and said MOSFETs have drains which are connected in common to said output line, and means for applying voltage to the sources of said MOSFETs.
Claim 5
Dependent Claim
68 words
The invention according to claim 1 wherein said MOSFETs have means for tunneling injection of charge into their floating gates, and programming means comprise means for applying signals of selected amplitude and duration to programming lines to floating gates of said MOSFETs to operate said charge injection means whereby the storage of said charge shifts the voltage thresholds of the MOSFETs, said stored charge providing the synaptic weights.
Claim 6
Dependent Claim
31 words
The invention according to claim 3 wherein the output line of each of said plurality of synapses are connected to a current summing node of said neuron at an input thereof.
Claim 7
Dependent Claim
75 words
The invention according to claim 1, wherein said network has a plurality of neurons fully connected, by connections of each said neurons to each other, interconnection points between said synapses and said neurons providing nodes, and wherein the number of neurons is M and the number of said synapses is M(M-1), the number of connections between said synapses and said neurons in said network is M 2 , and the number of nodes is M(M+1).
Claim 8
Dependent Claim
42 words
The invention according to claim 5 wherein said neuron provides an active load in the input of said neuron, and means for biasing said load to provide both inhibitory and excitatory output current on said output line from each of said synapses.
Claim 9
Dependent Claim
57 words
The invention according to claim 7 wherein said functions describes the operating regions of said synapse as defined by the input voltage, the weight of each said MOSFET, and the voltage at the output of the synapse, and by the voltage bias at the sources of said MOSFETs to provide either two or four quadrant operating modes.
Claim 10
Dependent Claim
91 words
The invention according to claim 8, wherein the sources of said MOSFETs in the synapses are biased at polarities opposite to each other, and the output of said synapse is connected to an active load in the input of said neuron, said active load comprises two complementary FETs, one of P-type and one of N-type, having gates and drains connected to the output of said synapse, and the sources of each said FETs are biased at opposite polarities, thereby providing the four quadrant operating mode of said synapse through said function.
Claim 11
Dependent Claim
105 words
A synapse connectable to a neuron in an artifical neural network which comprises a pair of MOSFETs of opposite conductivity type, each having source, drain, and gate electrodes, an operating voltage supply, a signal input connected in common to said gates, and said drains being connected in common to provide an output connectable to said neuron, said supply being connected across the said sources to connect said MOSFETs in an inverter configuration wherein said MOSFETs are P and N type, floating gate MOSFETs, with tunneling injection, and floating gate electrodes, and wherein programming lines are connected to said floating gate electrodes for carrying programming pulses.
Claim 12
Dependent Claim
105 words
A synapse connectable to a neuron in an artifical neural network which comprises a pair of MOSFETs of opposite conductivity type, each having source, drain, and gate electrodes, an operating voltage supply, a signal input connected in common to said gates, and said drains being connected in common to provide an output connectable to said neuron, said supply being connected across the said sources to connect said MOSFETs in an inverter configuration wherein said MOSFETs are P and N type, floating gate MOSFETs, with tunneling injection, and floating gate electrodes, and wherein programming lines are connected to said floating gate electrodes for carrying programming pulses.
Claim 13
Dependent Claim
30 words
The synapse according to claim 10, further comprises analog switches in said programming lines and, means for enabling said switches to apply said programming pulses to said floating gate electrodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |