Patent US5336632A successfully refreshed from Google Patents.
US5336632A
Expired / Lapsed
US
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Method for manufacturing capacitor and bipolar transistor
Assignee: NEC Corp
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Filing: 1993-07-27
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Granted: 1994-08-09
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Expires: 2013-07-27
Abstract
Abstract A lower electrode of a capacitor is manufactured simultaneously with an electrode such as a collector electrode and a base electrode of a bipolar transistor, and an upper electrode of the capacitor is manufactured simultaneously with another electrode such as an emitter electrode of the bipolar transistor. A dielectric layer between the lower and upper electrodes is manufactured simultaneously with other insulating layers of the bipolar transistor.
Inventors
- 👤 Hironobu Imamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:05
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
154 words
A method for manufacturing a capacitor and a bipolar transistor by using a semiconductor substrate including a capacitor forming area and a bipolar transistor forming area, comprising the steps of: forming a first insulating layer on the capacitor forming area of said semiconductor substrate; forming a capacitor lower electrode on said first insulating layer and, at least one of first and second electrodes of said bipolar transistor on the bipolar transistor forming area of said semiconductor substrate; forming a plurality of second insulating layers on said capacitor lower electrode and said first electrode; removing at least one of said plurality of second insulating layers on said capacitor lower electrode to form a capacitor dielectric layer by the remainder of said plurality of second insulating layers; and forming a capacitor upper electrode on said capacitor dielectric layer and a third electrode of said bipolar transistor on the bipolar transistor forming area of said semiconductor substrate.
Claim 2
Independent Claim
154 words
A method for manufacturing a capacitor and a bipolar transistor by using a semiconductor substrate including a capacitor forming area and a bipolar transistor forming area, comprising the steps of: forming a first insulating layer on the capacitor forming area of said semiconductor substrate; forming a capacitor lower electrode on said first insulating layer and, at least one of first and second electrodes of said bipolar transistor on the bipolar transistor forming area of said semiconductor substrate; forming a plurality of second insulating layers on said capacitor lower electrode and said first electrode; removing at least one of said plurality of second insulating layers on said capacitor lower electrode to form a capacitor dielectric layer by the remainder of said plurality of second insulating layers; and forming a capacitor upper electrode on said capacitor dielectric layer and a third electrode of said bipolar transistor on the bipolar transistor forming area of said semiconductor substrate.
Claim 3
Dependent Claim
52 words
A method as set forth in claim 1, wherein said plurality of second insulating layers comprises a first silicon nitride layer, a silicon dioxide layer and a second silicon nitride layer in this order, said removing step comprising a step of removing said silicon dioxide layer and said second silicon nitride layer.
Claim 4
Dependent Claim
27 words
A method as set forth in claim 1, wherein said first, second and third electrodes are a collector electrode, a base electrode and an emitter electrode, respectively.
Claim 5
Independent Claim
213 words
A method for manufacturing a capacitor and a bipolar transistor by using a semiconductor substrate including a capacitor forming area and a bipolar transistor forming area, comprising the steps of: forming a first insulating layer on the capacitor forming area of said semiconductor substrate; forming a second insulating layer on the bipolar transistor forming area of said semiconductor substrate; forming a capacitor lower electrode on said first insulating layer, a collector electrode of said bipolar transistor on the bipolar transistor forming area of said semiconductor substrate, and a base electrode of said bipolar transistor on said second insulating layer; forming third, fourth and fifth insulating layers in this order; selectively removing said third fourth and fifth insulating layers to expose a part of said base electrode; removing the exposed part of said base electrode; forming a graft base region, within said semiconductor substrate, connected to said base electrode; forming a base region, within said semiconductor substrate, connected to said graft base region; selectively removing said fourth and fifth insulating layers on said capacitor lower electrode to form a capacitor dielectrode layer by said second insulating layer; and forming a capacitor upper electrode on said capacitor dielectric layer and an emitter electrode of said bipolar transistor on the removed part of said base electrode.
Claim 6
Independent Claim
213 words
A method for manufacturing a capacitor and a bipolar transistor by using a semiconductor substrate including a capacitor forming area and a bipolar transistor forming area, comprising the steps of: forming a first insulating layer on the capacitor forming area of said semiconductor substrate; forming a second insulating layer on the bipolar transistor forming area of said semiconductor substrate; forming a capacitor lower electrode on said first insulating layer, a collector electrode of said bipolar transistor on the bipolar transistor forming area of said semiconductor substrate, and a base electrode of said bipolar transistor on said second insulating layer; forming third, fourth and fifth insulating layers in this order; selectively removing said third fourth and fifth insulating layers to expose a part of said base electrode; removing the exposed part of said base electrode; forming a graft base region, within said semiconductor substrate, connected to said base electrode; forming a base region, within said semiconductor substrate, connected to said graft base region; selectively removing said fourth and fifth insulating layers on said capacitor lower electrode to form a capacitor dielectrode layer by said second insulating layer; and forming a capacitor upper electrode on said capacitor dielectric layer and an emitter electrode of said bipolar transistor on the removed part of said base electrode.
Claim 7
Dependent Claim
33 words
A method as set forth in claim 4, wherein said third, fourth and fifth insulating layers comprise a first silicon nitride layer, a silicon dioxide layer and a second silicon nitride layer, respectively.
Claim 8
Dependent Claim
107 words
A method as set forth in claim 4, wherein said graft base region forming step comprises the steps of: doping impurities into said base electrode; forming a sidewall spacer covering a side of said third, fourth and fifth insulating layers at the removed portions thereof and a side of said base electrode at the removed portion thereof; removing a part of said second insulating layer with a mask of said sidewall spacer; filling non-doped conductive material into the side of said base electrode; and carrying out a heating operation to diffuse the impurities of said base electrode via the filled non-doped conductive material to said semiconductor substrate.
Claim 9
Dependent Claim
50 words
A method as set forth in claim 6, wherein said sidewall spacer forming step comprises the steps of: etching said fourth insulating layer with a mask of said base electrode and said third and fourth insulating layers; forming a sixth insulating layer thereon; and etching back said sixth insulating layer.
Claim 10
Dependent Claim
66 words
A method as set forth in claim 4, wherein said base region forming step comprises the steps of: forming a seventh insulating layer on said semiconductor substrate; doping impurities into said seventh insulating layer; form an eighth insulating layer on said seventh insulating layer; and performing a heat operation upon the impurities within said seventh insulating layer, to thereby diffuse the impurities into said semiconductor substrate.
References Cited (Backward Citations)
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