Patent DE7433012U successfully refreshed from Google Patents.
Patent US5336629A successfully refreshed from Google Patents.
US5336629A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors
Assignee: International Business Machines Corp
•
Filing: 1992-11-13
•
Granted: 1994-08-09
•
Expires: 2012-11-13
Abstract
Abstract A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.
Inventors
- 👤 Sang H. Dhong
- 👤 Wei Hwang
- 👤 Lewis M. Terman
- 👤 Matthew R. Wordeman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:50
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/373
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
132 words
A method for fabricating folded bitline DRAM cells on a semiconductor substrate in which a plurality of trench capacitors have been formed, the method comprising the steps of: depositing a planar semiconductor region that partially overlaps and spans a pair of adjacent trench capacitors; forming at least first, second and third contact areas within said planar semiconductor region, at least said first and second contact areas arrayed at extremities of said planar semiconductor region and in contact with terminals of said adjacent trench capacitors; constructing a bitline stud in contact with said third contact area; depositing a pair of gate structures between said third contact area and said first and second contact areas, respectively; and producing wordlines that contact said gate structures, and passing wordlines that are insulated from said gate structures.
Claim 2
Independent Claim
132 words
A method for fabricating folded bitline DRAM cells on a semiconductor substrate in which a plurality of trench capacitors have been formed, the method comprising the steps of: depositing a planar semiconductor region that partially overlaps and spans a pair of adjacent trench capacitors; forming at least first, second and third contact areas within said planar semiconductor region, at least said first and second contact areas arrayed at extremities of said planar semiconductor region and in contact with terminals of said adjacent trench capacitors; constructing a bitline stud in contact with said third contact area; depositing a pair of gate structures between said third contact area and said first and second contact areas, respectively; and producing wordlines that contact said gate structures, and passing wordlines that are insulated from said gate structures.
Claim 3
Dependent Claim
104 words
The method as recited in claim 1 wherein said wordlines and passing wordlines are produced by the further steps of: creating a first mesa of insulating material adjacent each said gate structure; depositing a second insulating mesa at least partially on said first mesa, said second mesa overlapping a said gate structure; applying a conformal coating of conductive material over said second mesa and in contact with said gate structure; and subsequently removing aspects of said conductive, material that are parallel to a major surface of said substrate to leave vertical strap portions thereof, said vertical strap portions acting as wordlines and passing wordlines.
Claim 4
Dependent Claim
39 words
The method as recited in claim 2 wherein said planar semiconductor region is deposited in a recess in said adjacent trench capacitors, said first and second contact areas making electrical connection to rim portions of said trench capacitor terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |