US5334549A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BiCMOS process that supports merged devices
Assignee: Texas Instruments Inc
•
Filing: 1993-08-13
•
Granted: 1994-08-02
•
Expires: 2013-08-13
Abstract
Abstract A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18a. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18b. Emitter electrode 30 is separated from base region 26 by thick oxide 24. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may also comprises LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.
Inventors
- 👤 Robert H. Eklund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:03
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; Y; Y10; Y10S; Y10S148/00; Y10S148/123
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
172 words
A method for forming a semiconductor device comprising the steps of: a. forming a first insulator layer over a surface of a semiconductor body having a first well region; b. implanting a base region in a first portion of said first well region; c. forming an emitter electrode over said first insulator layer and said base region, wherein a portion of said emitter electrode extends through said first insulator layer to said base region; d. removing a portion of said first insulator layer not covered by said emitter electrode; e. growing a second insulator layer on the surface of said semiconductor body; f. forming a plurality of gate electrodes on said second insulator layer, wherein at least one of said gate electrodes is formed over said first well region; g. forming a plurality of source/drain regions at the surface of said semiconductor body, wherein a first one of said source/drain regions is formed between said at least one gate electrode and said emitter electrode, said first source/drain region contacting said base region.
Claim 2
Independent Claim
172 words
A method for forming a semiconductor device comprising the steps of: a. forming a first insulator layer over a surface of a semiconductor body having a first well region; b. implanting a base region in a first portion of said first well region; c. forming an emitter electrode over said first insulator layer and said base region, wherein a portion of said emitter electrode extends through said first insulator layer to said base region; d. removing a portion of said first insulator layer not covered by said emitter electrode; e. growing a second insulator layer on the surface of said semiconductor body; f. forming a plurality of gate electrodes on said second insulator layer, wherein at least one of said gate electrodes is formed over said first well region; g. forming a plurality of source/drain regions at the surface of said semiconductor body, wherein a first one of said source/drain regions is formed between said at least one gate electrode and said emitter electrode, said first source/drain region contacting said base region.
Claim 3
Dependent Claim
81 words
The method of claim 1 wherein said step of forming said emitter electrode comprises the steps of: a. etching said first insulator layer to expose a portion of said base region; b. forming a first doped conductive layer over the surface of said semiconductor body; c. depositing a nitride layer over said first conductive layer; and d. etching said nitride layer and said first conductive layer to form said emitter electrode and to expose a portion of said first insulator layer.
Claim 4
Dependent Claim
46 words
The method of claim 2, wherein said step of forming said gate electrodes comprises the step of: a. forming a second doped conductive layer over the surface of said semiconductor body; and b. etching said second doped conductive layer to form said plurality of gate electrodes.
Claim 5
Dependent Claim
19 words
The method of claim 3, wherein said first and second doped conductive layers comprise polysilicon implant doped after deposition.
Claim 6
Dependent Claim
18 words
The method of claim 3, wherein said first and second doped conductive layers comprise polysilicon doped in situ.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein said second insulator layer is grown at a temperature greater than 850° C.
Claim 8
Dependent Claim
45 words
The method of claim 1, further comprising the steps of: a. implanting lightly doped drains on opposite sides of each gate electrode after said step of forming said gate electrodes; and b. forming sidewall dielectrics adjacent each of said gate electrodes and said emitter electrode.
Claim 9
Dependent Claim
18 words
The method of claim 1, further comprising the step of siliciding said emitter electrode and said gate electrodes.
Claim 10
Dependent Claim
88 words
The method of claim 8, wherein said step of siliciding said emitter electrode and said gate electrodes comprises the steps of: a. depositing a layer of refractory metal over the surface of said semiconductor body; b. annealing said layer of refractory metal in a nitrogen containing ambient to form a layer of silicide over said emitter electrode and said gate electrodes and a layer of refractory metal-nitride or unreacted metal where said silicide layer is not formed; and c. etching said layer of refractory metal-nitride or unreacted metal.
Claim 11
Dependent Claim
35 words
The method of claim 1, wherein said step of forming said source/drain regions comprises the steps of: a. implanting said source/drain regions; and b. annealing said source/drain regions at a temperature less than 900° C.
Claim 12
Dependent Claim
33 words
The method of claim 1, wherein said first insulator layer comprises oxide on the order of 300 Å thick and said second insulator layer comprises oxide on the order of 100 Å thick.
Claim 13
Independent Claim
271 words
A method of forming a BiCMOS device comprising the steps of: a. forming a plurality of field insulating regions at a surface of a semiconductor body having a first well region; b. forming a thick oxide layer over said surface of said semiconductor body; c. implanting a base region through said thick oxide layer in a first portion of said first well region adjacent a first one of said field insulating regions; d. etching said thick oxide layer to expose a portion of said base region; e. depositing a first layer of polysilicon over said thick oxide layer and said exposed portion of said base region; f. depositing a layer of nitride over said first polysilicon layer; g. etching said nitride layer and said first polysilicon layer to form an emitter electrode over said base region and to expose a portion of said thick oxide layer; h. removing said exposed portion of said thick oxide layer; i. growing a gate oxide layer over the surface of said semiconductor body; j. depositing a second layer of polysilicon over said gate oxide layer; k. etching said second polysilicon layer to form a plurality of gate electrodes, wherein at least one of said gate electrodes is formed over said first well region; l. implanting lightly doped drain regions at the surface of said semiconductor body on opposite sides of each gate electrode; m. forming sidewall oxides adjacent said gate electrodes and said emitter electrode; n. implanting source/drain regions at the surface of said semiconductor body on opposite sides of each gate electrode; o. annealing said source/drain regions at a temperature less than 900° C.
Claim 14
Independent Claim
271 words
A method of forming a BiCMOS device comprising the steps of: a. forming a plurality of field insulating regions at a surface of a semiconductor body having a first well region; b. forming a thick oxide layer over said surface of said semiconductor body; c. implanting a base region through said thick oxide layer in a first portion of said first well region adjacent a first one of said field insulating regions; d. etching said thick oxide layer to expose a portion of said base region; e. depositing a first layer of polysilicon over said thick oxide layer and said exposed portion of said base region; f. depositing a layer of nitride over said first polysilicon layer; g. etching said nitride layer and said first polysilicon layer to form an emitter electrode over said base region and to expose a portion of said thick oxide layer; h. removing said exposed portion of said thick oxide layer; i. growing a gate oxide layer over the surface of said semiconductor body; j. depositing a second layer of polysilicon over said gate oxide layer; k. etching said second polysilicon layer to form a plurality of gate electrodes, wherein at least one of said gate electrodes is formed over said first well region; l. implanting lightly doped drain regions at the surface of said semiconductor body on opposite sides of each gate electrode; m. forming sidewall oxides adjacent said gate electrodes and said emitter electrode; n. implanting source/drain regions at the surface of said semiconductor body on opposite sides of each gate electrode; o. annealing said source/drain regions at a temperature less than 900° C.
Claim 15
Dependent Claim
21 words
The method of claim 12, further comprising the step of siliciding said emitter electrode, said gate electrodes, and said source/drain regions.
Claim 16
Dependent Claim
88 words
The method of claim 13, wherein said step of siliciding said emitter electrode, said gate electrodes, and said source/drain regions comprises the steps of: a. depositing a layer of refractory metal over the surface of said semiconductor body; b. annealing said layer of refractory metal in a nitrogen containing ambient to forme a layer of silicide over said emitter electrode, said gate electrodes, and said source/drain regions and a layer of refractory metal-nitride or unreacted metal elsewhere; and c. etching said layer of refractory metal-nitride or unreacted metal.
References Cited (Backward Citations)
US4495376A
Cited
US4541167A
Cited
US4958213A
Cited
US5171702A
Cited
US5262345A
Cited
US4987089A
Cited
US5028557A
Cited
US5171699A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-01 | 1998-01-31 | 1998-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-01 | 2002-01-31 | 2002-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-01 | 2006-01-31 | 2006-08-02 | $7700.00 | Window Closed / Lapsed |