Patent US5333293A successfully refreshed from Google Patents.
US5333293A
Expired / Lapsed
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Multiple input frequency memory controller
Assignee: Hewlett Packard Development Co LP
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Filing: 1991-09-11
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Granted: 1994-07-26
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Expires: 2011-09-11
Abstract
Abstract A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.
Inventors
- 👤 Randy M. Bonella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:54
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
221 words
A computer system comprising: a central processor unit operating at one of a plurality of designated frequencies and having address, data and control buses; a reference clock having a frequency related to said central processor unit operating frequency; dynamic random access memory having address and data buses and control inputs; buffer and latch units having data buses coupled to said central processor unit data bus and said memory data bus and having latch and output control inputs; means for indicating central processor unit operating frequency; and a memory controller having address and control inputs coupled to said central processor unit address and control buses, having control output coupled to said memory control inputs and said buffer and latch unit latch and output control inputs, having an input coupled to said reference clock, and having an input coupled to said operating frequency indicating means, said memory controller utilizing a plurality of different reference clock frequencies and central processor unit operating frequencies so that said memory controller control outputs are provided at approximately the same time and duration for each of said central processor unit operating frequencies, wherein said memory controller operates synchronously using a state machine, wherein various states are bypassed based on said central processor unit operating frequency and wherein said memory controller state machine is advanced by said reference clock.
Claim 2
Dependent Claim
221 words
A computer system comprising: a central processor unit operating at one of a plurality of designated frequencies and having address, data and control buses; a reference clock having a frequency related to said central processor unit operating frequency; dynamic random access memory having address and data buses and control inputs; buffer and latch units having data buses coupled to said central processor unit data bus and said memory data bus and having latch and output control inputs; means for indicating central processor unit operating frequency; and a memory controller having address and control inputs coupled to said central processor unit address and control buses, having control output coupled to said memory control inputs and said buffer and latch unit latch and output control inputs, having an input coupled to said reference clock, and having an input coupled to said operating frequency indicating means, said memory controller utilizing a plurality of different reference clock frequencies and central processor unit operating frequencies so that said memory controller control outputs are provided at approximately the same time and duration for each of said central processor unit operating frequencies, wherein said memory controller operates synchronously using a state machine, wherein various states are bypassed based on said central processor unit operating frequency and wherein said memory controller state machine is advanced by said reference clock.
Claim 3
Dependent Claim
47 words
The computer system of claim 1, wherein for at least one central processor unit operating frequency said reference clock is a multiple of said operating frequency, and for at least one central processor unit operating frequency said reference clock is the same frequency as said operating frequency.
Claim 4
Dependent Claim
73 words
The computer system of claim 1, further comprising: an external, standardized bus having address, data and control portions; and means for coupling said external bus to said central processor unit and said dynamic random access memory; and wherein said memory controller is coupled to said external bus control portion to provide control to said dynamic random access memory and said buffer and latch unit when control signals are being over said external bus.
Claim 5
Dependent Claim
29 words
The computer system of claim 3, wherein said memory controller operates synchronously using a state machine and wherein various states are bypassed based on central processor unit operating frequency.
Claim 6
Dependent Claim
26 words
The computer system of claim 4, wherein said memory controller includes separate state machines for operation with said central processor unit and with said external bus.
Claim 7
Dependent Claim
47 words
The computer system of claim 5, wherein for at least one central processor unit operating frequency said reference clock is a multiple of said operating frequency, and for at least one control processor unit operating frequency said reference clock is the same frequency as said operating frequency.
Claim 8
Dependent Claim
18 words
The computer system of claim 3, wherein said memory controller state machine is advanced by said reference clock.
Claim 9
Dependent Claim
19 words
The computer system of claim 1, wherein said central processor unit operating frequencies include 16, 25 and 33 MHz.
Claim 10
Dependent Claim
17 words
The computer system of claim 8, wherein said reference clock frequencies include 32, 25 and 33 MHz.
References Cited (Backward Citations)
US4014006A
Cited
US4095267A
Cited
US4821229A
Cited
US5086387A
Cited
US5097437A
Cited
US5179667A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |