Semiconductor memory device having a circuit for reducing frequency of proceeding refresh in data retention mode

Claim 2

A semiconductor memory device comprising: a memory including a plurality of word lines for accessing data stored in the memory; a refresh cycle controller for controlling the frequency of the refresh cycles in data retention mode based upon at least one row address bit and a self-refresh signal, the refresh cycle controller comprising means for separately gating said at least one row address bit and a complement of said at least one row address bit and a complement of said at least one row address bit in response to said self-refresh signal; and a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal.

Claim 3

A semiconductor memory device as in claim 1, wherein said gating means include: a first inverter having an input terminal receiving said self refresh signal; a first NAND logic circuit having input terminals respectively connected to said at least one row address bit and an output terminal of said first inverter; and a second NAND logic circuit having input terminals respectively connected to a complement of said at least one row address bit and the output terminal of said first inverter.

Claim 4

A semiconductor memory device as in claim 1, wherein said gating means includes: a first inverter having an input terminal receiving said self-refresh signal; a first NAND gate having input terminals respectively connected to said at least one row address bit and an output terminal of said first inverter; a second NAND gate having input terminals respectively connected to a complement of said at least one row address bit and the output terminal of said first inverter; a second inverter having an input terminal connected to an output terminal of the first NAND gate; and a third inverter having an input terminal connected to an output terminal of the second NAND gate.

Claim 5

A semiconductor memory device comprising: a memory including a plurality of word lines for accessing data stored in the memory; a refresh cycle controller for controlling the frequency of refresh cycles in data retention mode based on at least one row address bit and a self-refresh signal; and a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal, said word line boosting level generator comprising: a fourth inverter receiving said self-refresh signal; a fifth inverter receiving said clock-enable signal; a sixth inverter having an input terminal connected to an output terminal of said fifth inverter; a transmission gate having a control terminal connected between the self-refresh signal and an output terminal of the fourth inverter, and an input terminal connected to an output terminal of the sixth inverter; a first field effect transistor having a gate terminal connected to the output terminal of the fourth inverter, a drain terminal connected to a voltage supply Vcc, and a source terminal connected to an output terminal of the transmission gate; a second field effect transistor having a drain terminal connected to the voltage supply Vcc and a gate terminal and a source terminal connected to the output terminal of the transmission gate; a first metal oxide semiconductor capacitor having one terminal connected to the output terminal of the transmission gate; a second metal oxide semiconductor capacitor having one terminal connected to the output terminal of the sixth inverter, and another terminal connected to another terminal of the first MOS capacitor; a third field effect transistor having a drain terminal connected to the voltage supply Vcc, a gate terminal connected to a precharge signal line, and a source terminal connected to a node formed by said another terminals respectively of the first and second metal oxide semiconductor capacitors; and a fourth field effect transistor having a drain terminal connected to the node of the first and second metal oxide semiconductor capacitors, a source terminal connected to a voltage supply Vss, and a gate terminal connected to an output disable signal.

Claim 6

A semiconductor memory device comprising: a memory including a plurality of word lines for accessing data stored in the memory; a refresh cycle controller for controlling the frequency of refresh cycles in data retention mode based on at least one row address bit and a self-refresh signal; and a word line boosting level generator for increasing a boosting level of said word lines to said memory in data retention mode in response to said self-refresh signal and a clock-enable signal, said word line boosting level generator comprising: a fourth inverter receiving said self-refresh signal; a fifth inverter receiving said clock-enable signal; a sixth inverter having an input terminal connected to an output terminal of said fifth inverter; a transmission gate having a control terminal connected between the self-refresh signal and an output terminal of the fourth inverter, and an input terminal connected to an output terminal of the sixth inverter; a first field effect transistor having a gate terminal connected to the output terminal of the fourth inverter, a drain terminal connected to a voltage supply Vcc, and a source terminal connected to an output terminal of the transmission gate; a second field effect transistor having a drain terminal connected to the voltage supply Vcc and a gate terminal and a source terminal connected to the output terminal of the transmission gate; a first metal oxide semiconductor capacitor having one terminal connected to the output terminal of the transmission gate; a second metal oxide semiconductor capacitor having one terminal connected to the output terminal of the sixth inverter, and another terminal connected to another terminal of the first MOS capacitor; a third field effect transistor having a drain terminal connected to the voltage supply Vcc, a gate terminal connected to a precharge signal line, and a source terminal connected to a node formed by said another terminals respectively of the first and second metal oxide semiconductor capacitors; and a fourth field effect transistor having a drain terminal connected to the node of the first and second metal oxide semiconductor capacitors, a source terminal connected to a voltage supply Vss, and a gate terminal connected to an output disable signal.