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US5332935A Expired / Lapsed US ⏱️ 0.0 years remaining

ECL and TTL to CMOS logic converter

Assignee: Microsemi Storage Solutions Inc
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Filing: 1993-04-12
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Granted: 1994-07-26
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Expires: 2013-04-12
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Abstract

Abstract A logic converter enables a digital logic product to work with either an ECL signal input or a TTL signal input without any need of modifying or reconfiguring the product. In particular, the logic converter converts digital input signals of a first logic type (for example, ECL) to digital output signals of a third logic type (for example, CMOS). It also converts digital input signals of a second logic type (for example, TTL) to digital output signals of the third logic type. A first operational transconductance amplifier circuit including a first differential amplifier using a differential transistor pair of a first conduction type receives digital input signals of the first logic type and converts the digital input signals to digital output signals of the third logic type. A second operational transconductance amplifier circuit including a second differential amplifier using a differential transistor pair of a second conduction type receives digital input signals of the second logic type and converts the digital input signals to digital output signals of the third logic type. Circuitry causes only one of the first differential amplifier and the second differential amplifier to be active at a time depending on which logic type of digital input signal is being received. The circuitry for causing only one differential amplifier to be active includes a first level shifting circuit connected to the first differential amplifier and a second level shifter circuit connected to the second differential amplifier.

Inventors

  • 👤 Jyn-Bang Shyu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 11:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 166 words
Apparatus for converting digital input signals of a first logic type to digital output signals of a third logic type and also for converting digital input signals of a second logic type to digital output signals of said third logic type, comprising: first operational transconductance amplifier means, including a first differential amplifier using a differential transistor pair of a first conduction type, for receiving digital input signals of said first logic type and converting the digital input signals to digital output signals of said third logic type; second operational transconductance amplifier means, including a second differential amplifier using a differential transistor pair of a second conduction type, for receiving digital input signals of said second logic type and converting the digital input signals to digital output signals of said third logic type; and means for causing only one of said first differential amplifier and said second differential amplifier to be active at a time depending on which logic type of digital input signals is being received.
Claim 2
Dependent Claim 166 words
Apparatus for converting digital input signals of a first logic type to digital output signals of a third logic type and also for converting digital input signals of a second logic type to digital output signals of said third logic type, comprising: first operational transconductance amplifier means, including a first differential amplifier using a differential transistor pair of a first conduction type, for receiving digital input signals of said first logic type and converting the digital input signals to digital output signals of said third logic type; second operational transconductance amplifier means, including a second differential amplifier using a differential transistor pair of a second conduction type, for receiving digital input signals of said second logic type and converting the digital input signals to digital output signals of said third logic type; and means for causing only one of said first differential amplifier and said second differential amplifier to be active at a time depending on which logic type of digital input signals is being received.
Claim 3
Dependent Claim 37 words
The apparatus of claim 1 wherein said means for causing only one differential amplifier to be active comprises first level-shifting means connected to said first differential amplifier and second level-shifting means connected to said second differential amplifier.
Claim 4
Dependent Claim 12 words
The apparatus of claim 2 wherein said third logic type is CMOS.
Claim 5
Dependent Claim 13 words
The apparatus of claim 3 wherein said first logic type is modified ECL.
Claim 6
Dependent Claim 12 words
The apparatus of claim 3 wherein said second logic type is TTL.
Claim 7
Dependent Claim 42 words
The apparatus of claim 5 wherein said digital input signals of said second logic type comprise a signal pair, one signal of the signal pair being a standard TTL signal and another signal of the signal pair being a constant-level D.C. signal.
Claim 8
Dependent Claim 16 words
The apparatus of claim 6 wherein the constant-level D.C. signal is a TTL common mode voltage.

References Cited (Backward Citations)

US4472647A Cited
US4625129A Cited
US4527079A Cited
US5034634A Cited
US4975602A Cited
US5166558A Cited
US5260612A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-07-25 1998-01-24 1998-07-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-07-25 2002-01-24 2002-07-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-07-25 2006-01-24 2006-07-26 $7700.00 Window Closed / Lapsed

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