US5332933A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar-MOS circuits with dimensions scaled to enhance performance
Assignee: HP Inc
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Filing: 1993-01-21
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Granted: 1994-07-26
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Expires: 2013-01-21
Abstract
Abstract An optimum ratio relating the characteristic dimensions of the MOS pull-up and the MOS pull-down devices of a logic circuit with one or more bipolar devices connected to an output of the circuit. This optimum ratio substantially minimizes the propagation delay of the circuit. The first preferred embodiment is shown in a BiNMOS circuit, and the second preferred embodiment is shown in a BiCMOS circuit.
Inventors
- 👤 Prasad A. Raje
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/01
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
206 words
A logic circuit comprising: a pull-up section including bipolar pull-up means connected between a first terminal and an output of the circuit; MOS pull-up means, characterized by a first dimension, driving the bipolar pull-up means and responding to an input signal to force the bipolar pull-up means to provide a low resistance current path for establishing a first logic level at the output if the input signal assumes a second logic level; and a pull-down section including MOS pull-down means, characterized by a second dimension, connected between the output of the circuit and a second terminal, the MOS pull-down means responding to the input signal to provide a low resistance current path for establishing the second logic level at the output if the input signal assumes the first logic level, such that the first and the second dimension are elated by an optimum ratio that substantially minimizes a propagation delay of the circuit; the sum of the first and the second dimension is proportional to an input capacitance of the circuit; and the optimum ratio is independent of a fanout which is defined as a load capacitance of the circuit divided by the input capacitance, the load capacitance being connected to the output of the circuit.
Claim 2
Dependent Claim
206 words
A logic circuit comprising: a pull-up section including bipolar pull-up means connected between a first terminal and an output of the circuit; MOS pull-up means, characterized by a first dimension, driving the bipolar pull-up means and responding to an input signal to force the bipolar pull-up means to provide a low resistance current path for establishing a first logic level at the output if the input signal assumes a second logic level; and a pull-down section including MOS pull-down means, characterized by a second dimension, connected between the output of the circuit and a second terminal, the MOS pull-down means responding to the input signal to provide a low resistance current path for establishing the second logic level at the output if the input signal assumes the first logic level, such that the first and the second dimension are elated by an optimum ratio that substantially minimizes a propagation delay of the circuit; the sum of the first and the second dimension is proportional to an input capacitance of the circuit; and the optimum ratio is independent of a fanout which is defined as a load capacitance of the circuit divided by the input capacitance, the load capacitance being connected to the output of the circuit.
Claim 3
Dependent Claim
29 words
A plurality of logic circuits, each logic circuit as recited in claim 1 wherein: the optimum ratio is substantially the same in at least two of the logic circuits.
Claim 4
Dependent Claim
39 words
A plurality of logic circuits, each logic circuit as recited in claim 1 wherein: the optimum ratio is substantially the same in at least two of the logic circuits; and the optimum ratio is independent of the input capacitance.
Claim 5
Dependent Claim
49 words
A plurality of logic circuits, each logic circuit as recited in claim 1 wherein: the optimum ratio is substantially the same in at least two of the logic circuits; the bipolar pull-up means is characterized by a third dimension; and the optimum ratio is independent of the third dimension.
Claim 6
Dependent Claim
37 words
A logic circuit as in claim 1 wherein: the bipolar pull-up means comprises a bipolar transistor which has a base and an emitter; and the MOS pull-down means comprises a NMOS pull-down transistor which has a gate.
Claim 7
Dependent Claim
91 words
A logic circuit as in claim 5 wherein: the MOS pull-up means comprises a PMOS pull-up transistor and a NMOS pull-up transistor; the PMOS pull-up transistor has a gate and operates to establish a low resistance current path between the first terminal and the base of the bipolar transistor if the input signal assumes the first logic level; and the NMOS pull-up transistor operates to establish a low resistance current path between the second terminal and the base of the bipolar transistor if the input signal assumes the second logic level.
Claim 8
Dependent Claim
64 words
A logic circuit as in claim 6 wherein: the bipolar transistor comprises a NPN transistor; the first dimension is the width of the gate of the PMOS pull-up transistor; the second dimension is the width of the gate of the NMOS pull-down transistor; the bipolar transistor is characterized by the length of its emitter; and the optimum ratio is independent of the emitter length.
Claim 9
Dependent Claim
163 words
A logic circuit comprising: a pull-up section including bipolar pull-up means connected between a first terminal and an output of the circuit; MOS pull-up means, characterized by a first dimension, driving the bipolar pull-up means and responding to an input signal to force the bipolar pull-up means to provide a low resistance current path for establishing a first logic level at the output if the input signal assumes a second logic level; and a pull-down section including bipolar pull-down means connected between a second terminal and the output of the circuit; and MOS pull-down means, characterized by a second dimension, driving the bipolar pull-down means and responding to the input signal to force the bipolar pull-down means to provide a low resistance current path for establishing the second logic level at the output if the input signal assumes the first logic level, the first and the second dimension being related by an optimum ratio that substantially minimizes a propagation delay of the circuit.
Claim 10
Dependent Claim
163 words
A logic circuit comprising: a pull-up section including bipolar pull-up means connected between a first terminal and an output of the circuit; MOS pull-up means, characterized by a first dimension, driving the bipolar pull-up means and responding to an input signal to force the bipolar pull-up means to provide a low resistance current path for establishing a first logic level at the output if the input signal assumes a second logic level; and a pull-down section including bipolar pull-down means connected between a second terminal and the output of the circuit; and MOS pull-down means, characterized by a second dimension, driving the bipolar pull-down means and responding to the input signal to force the bipolar pull-down means to provide a low resistance current path for establishing the second logic level at the output if the input signal assumes the first logic level, the first and the second dimension being related by an optimum ratio that substantially minimizes a propagation delay of the circuit.
Claim 11
Dependent Claim
82 words
A plurality of logic circuits, each logic circuit as recited in claim 8 wherein: the optimum ratio is substantially the same in at least two of the logic circuits; the sum of the first and the second dimension is proportional to an input capacitance of the circuit; and the optimum ratio is independent of a fanout which is defined as a load capacitance of the circuit divided by the input capacitance, the load capacitance being connected to the output of the circuit.
Claim 12
Dependent Claim
57 words
A plurality of logic circuits, each logic circuit as recited in claim 8 wherein: the optimum ratio is substantially the same in at least two of the logic circuits; the sum of the first and the second dimension is proportional to an input capacitance of the circuit; and the optimum ratio is independent of the input capacitance.
Claim 13
Dependent Claim
59 words
A plurality of logic circuits, each logic circuit as recited in claim 8 wherein: the optimum ratio is substantially the same in at least two of the logic circuits; the bipolar pull-up means is substantially the same as the bipolar pull-down means and is characterized by a third dimension; and the optimum ratio is independent of the third dimension.
Claim 14
Dependent Claim
41 words
A logic circuit as in claim 8 wherein the bipolar pull-up means comprises a bipolar pull-up transistor which has a base and an emitter; and the bipolar pull-down means comprises a bipolar pull-down transistor which has a base and an emitter.
Claim 15
Dependent Claim
194 words
A logic circuit as in claim 12 wherein: the MOS pull-up means comprises a PMOS pull-up transistor and a NMOS pull-up transistor; the PMOS pull-up transistor has a gate and operates to establish a low resistance current path between the first terminal and the base of the bipolar pull-up transistor if the input signal assumes the first logic level; the NMOS pull-up transistor operates to establish a low resistance current path between the second terminal and the base of the bipolar pull-up transistor if the input signal assumes the second logic level; the MOS pull-down means comprises a first NMOS pull-down transistor and a second NMOS pull-down transistor; the first NMOS pull-down transistor has a gate and operates to establish a low resistance current path between the output of the circuit and the base of the bipolar pull-down transistor if the input signal assumes the second logic level; and the second NMOS pull-down transistor operates to establish a low resistance current path between the base of the bipolar pull-down transistor and the second terminal if a low resistance current path is established between the first terminal and the base of the bipolar pull-up transistor.
Claim 16
Dependent Claim
81 words
A logic circuit as in claim 13 wherein: the bipolar pull-up and the bipolar pull-down transistor are both NPN transistors; the first dimension is the width of the gate of the PMOS pull-up transistor; the second dimension is the width of the gate of the first NMOS pull-down transistor; the bipolar pull-up transistor is substantially the same as the bipolar pull-down transistor, and is characterized by the length of its emitter; and the optimum ratio is independent of the emitter length.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |