High speed differential comparator

Claim 2

A differential comparator comprising: a first and a second input terminal for receiving first and second input signals, respectively, which are to be compared; first and second amplifying means, each amplifying means having an input and an output and further including selective coupling means for selectively coupling the input and output of the amplifying means for auto-zeroing the amplifying means; a first capacitor having a first plate connected to the first input terminal and a second plate connected to the input of the first amplifying means; a second capacitor having a first plate connected to the second input terminal and a second plate connected to the input of the second amplifying means; a third capacitor connected between the output of the first amplifying means and the input of the second amplifying means; a fourth capacitor connected between the output of the second amplifying means and the input of the first amplifying means; and first selective connecting means for selectively connecting the first plate of the first capacitor to the first plate of the second capacitor.

Claim 3

The differential comparator of claim 1 wherein the first and second input terminals receive the first and second input signals, respectively, concurrent with the first and second amplifying means being auto-zeroed.

Claim 4

The differential comparator of claim 2 wherein the first selective connecting means connects the first plate of the first capacitor to the first plate of the second capacitor after the first and second input signals have been received and the first and second amplifying means have been autozeroed.

Claim 5

The differential comparator of claim 3 wherein the differential comparator further comprises second selective connecting means for selectively isolating the first and second capacitors from the input of the first and second amplifiers, respectively, at a predetermined period of time after the first selective connecting means connects the first plate of the first capacitor to the first plate of the second capacitor.

Claim 6

A differential comparator comprising: a first and a second input terminal for receiving first and second input signals, respectively, which are to be compared; first and second amplifiers, each amplifier comprising an input and an output which is coupled to a separate output terminal of the differential comparator; a feedback network which capacitively couples the output of the first and the second amplifier to the input of the second and the first amplifier, respectively; first and second capacitors, each capacitor coupling a separate input terminal of the differential comparator to the input of a separate one of the first and second amplifiers; and switching means for selectively (a) precharging each of the first and second amplifiers to a separate predetermined value, (b) delivering the first and second input signals to the first and second capacitors, respectively, during a first phase of operation, and (c) isolating the first and second input terminals from the first and second capacitors and placing a short thereacross while releasing the first and second amplifiers from their precharged state during a second phase of operation to provide an indication of which input signal has a greater amplitude.

Claim 7

A differential comparator comprising: a first and a second input terminal for receiving first and second input signals, respectively, which are to be compared; first and second amplifiers, each amplifier comprising an input and an output which is coupled to a separate output terminal of the differential comparator; a feedback network which capacitively couples the output of the first and the second amplifier to the input of the second and the first amplifier, respectively; first and second capacitors, each capacitor coupling a separate input terminal of the differential comparator to the input of a separate one of the first and second amplifiers; and switching means for selectively (a) precharging each of the first and second amplifiers to a separate predetermined value, (b) delivering the first and second input signals to the first and second capacitors, respectively, during a first phase of operation, and (c) isolating the first and second input terminals from the first and second capacitors and placing a short thereacross while releasing the first and second amplifiers from their precharged state during a second phase of operation to provide an indication of which input signal has a greater amplitude.

Claim 8

The differential comparator of claim 5 wherein the switching means comprises: first gating means for selectively coupling the first and second input terminals of the differential comparator to the first and second capacitors, respectively; second gating means for selectively coupling the input to the output of each of the first and second amplifiers; and third gating means for selectively placing a short between an input terminal of each of the first and second capacitors which is coupled to the first gating means.

Claim 9

The differential comparator of claim 6 wherein during the first phase of operation: the first gating means is closed so as to couple the first and second input terminals of the differential comparator to the first and second capacitors, respectively, for impressing the first and second input signals onto the first and second capacitors, respectively; the second gating means is closed to provide a short across each of the first and second amplifiers to precharge each amplifier to a predetermined value; and the third gating means is opened so as to remove the short between the input terminals of the first and second capacitors.

Claim 10

The differential comparator of claim 7 wherein during the second phase of operation the first gating means is opened to isolate the first and second input terminals of the differential comparator from the first and second capacitors, the second gating means is opened to remove the short across each of the first and second amplifiers, and the third gating means is closed to provide a short between the input terminals of the first and second capacitors.

Claim 11

The differential comparator of claim 8 further comprising a fourth gating means for selectively isolating the first and second capacitors from the input of each of the first and second amplifiers at a predetermined period of time after the second phase of operation has begun.

Claim 12

The differential comparator of claim 9 wherein during the first phase of operation the fourth gating means is closed to couple the first and second capacitors to the input of the first and second amplifiers, respectively, and during the second phase of operation the fourth gating means remains closed for a predetermined period of time until a latching process has started in the feedback network and then the fourth gating means is opened to isolate the inputs of the first and second amplifiers from the first and second capacitors, respectively.

Claim 13

The differential comparator of claim 6 further comprising fourth gating means for selectively isolating the first and second capacitors from the input of each of the first and second amplifiers.

Claim 14

The differential comparator of claim 11 wherein during the first phase of operation the first gating means is closed to couple the first and second input terminals of the differential comparator to the first and second capacitors for impressing the first and second input signals thereon, the second gating means is closed to provide a short across each of the first and second amplifiers to precharge each amplifier to a predetermined value, and the third gating means is open to remove the short circuit between the input terminals of the first and second capacitors.

Claim 15

The differential comparator of claim 12 wherein during the second phase of operation the first gating means is opened to isolate the first and second input terminals of the differential comparator from the first and second capacitors, the second gating means is opened to remove the short across each of the first and second amplifiers, and the third gating means is closed to provide a short between the input terminal of the first and second capacitors.

Claim 16

A differential comparator comprising: first and second input terminals for receiving first and second input signals, respectively, which are to be compared; first and second amplifiers, each amplifier comprising an input and an output which is coupled to a separate output terminal of the differential comparator; a feedback network which capacitively couples the output of the first and the second amplifier to the input of the second and the first amplifier, respectively; first and second capacitors, each capacitor coupling a separate input terminal of the differential comparator to the input of a separate one of the first and second amplifiers; and switching means for selectively (a) precharging each of the first and second amplifiers to a separate predetermined value, and delivering the first and second input signals to the first and second capacitors, respectively, during a first phase of operation, (b) isolating the first and second input terminals from the first and second capacitors, and placing a short across an input terminal of the first and second capacitors while releasing the first and second amplifiers from their precharged state during a second phase of operation, and (c) isolating the first and second capacitors from the input of each of the first and second amplifiers when a latching of the first and second amplifiers has begun during the second phase of operation.

Claim 17

A differential comparator comprising: first and second input terminals for receiving first and second input signals, respectively, which are to be compared; first and second amplifiers, each amplifier comprising an input and an output which is coupled to a separate output terminal of the differential comparator; a feedback network which capacitively couples the output of the first and the second amplifier to the input of the second and the first amplifier, respectively; first and second capacitors, each capacitor coupling a separate input terminal of the differential comparator to the input of a separate one of the first and second amplifiers; and switching means for selectively (a) precharging each of the first and second amplifiers to a separate predetermined value, and delivering the first and second input signals to the first and second capacitors, respectively, during a first phase of operation, (b) isolating the first and second input terminals from the first and second capacitors, and placing a short across an input terminal of the first and second capacitors while releasing the first and second amplifiers from their precharged state during a second phase of operation, and (c) isolating the first and second capacitors from the input of each of the first and second amplifiers when a latching of the first and second amplifiers has begun during the second phase of operation.

Claim 18

The differential comparator of claim 14 wherein the switching means comprises: first gating means for selectively coupling the first and second input terminals of the differential comparator to the first and second capacitors, respectively; second gating means for selectively coupling the input and the output of each of the first and second amplifiers; third gating means for selectively placing a short circuit across an input terminal to each of the first and second capacitors which are coupled to the first gating means; and fourth gating means for selectively isolating the first and second capacitors from the input of each of the first and second amplifiers.

Claim 19

The differential comparator of claim 15 wherein during the first phase of operation: the first gating means is closed so as to couple the first and second input terminals of the differential comparator to the first and second capacitors, respectively, for impressing the first and second input signals onto the first and second capacitors, respectively; the second gating means is closed to provide a short circuit across each of the first and second amplifiers to precharge each amplifier to a predetermined value; and the third gating means is opened so as to remove the short circuit across the input terminals of the first and second capacitors.

Claim 20

The differential comparator of claim 16 wherein during the second phase of operation: the first gating means is opened so as to isolate the first and second input terminals of the differential comparator from the first and second capacitors; the second gating means is opened so as to remove the short across each of the first and second amplifiers; and the third gating means is closed so as to provide a short circuit across the input terminals of the first and second capacitors.

Claim 21

The differential comparator of claim 17 wherein during the first phase of operation the fourth gating means is closed so as to couple second terminal of the first and second capacitor to the input of the first and second amplifier, respectively, and during the second phase of operation the fourth gating means remains closed for a predetermined period of time until a latching process has started in the feedback network and then the fourth gating means is opened so as to isolate the input of the first and second amplifiers from the first and second capacitors, respectively.

Claim 22

Circuitry comprising: first and second inverters each having an input and an output; first, second, third, fourth and fifth switches each having first and second terminals; first, second, third and fourth capacitors each having first and second terminals; a first input circuitry terminal is coupled to the first terminal of the first switch; a second input circuitry terminal is coupled to the first terminal of the second switch; a second terminal of the first switch is coupled to the first terminals of the first capacitor and the third switch; a second terminal of the second switch is coupled to the first terminal of the second capacitor and to the second terminal of the third switch; a second terminal of the first capacitor is coupled to the first terminal of the fourth switch, to the first terminal of the fourth capacitor, and to the input of the first inverter; a second terminal of the second capacitor is coupled to the first terminal of the fifth switch, to the first terminal of the third capacitor, and to the input of the second inverter; the output of the first inverter is coupled to the second terminals of the fourth switch and the third capacitor, and to a first output terminal of the circuitry; and the output of the second inverter is coupled to the second terminals of the fifth switch and the fourth capacitor, and to a second output terminal of the circuitry.

Claim 23

Circuitry comprising: first and second inverters each having an input and an output; first, second, third, fourth and fifth switches each having first and second terminals; first, second, third and fourth capacitors each having first and second terminals; a first input circuitry terminal is coupled to the first terminal of the first switch; a second input circuitry terminal is coupled to the first terminal of the second switch; a second terminal of the first switch is coupled to the first terminals of the first capacitor and the third switch; a second terminal of the second switch is coupled to the first terminal of the second capacitor and to the second terminal of the third switch; a second terminal of the first capacitor is coupled to the first terminal of the fourth switch, to the first terminal of the fourth capacitor, and to the input of the first inverter; a second terminal of the second capacitor is coupled to the first terminal of the fifth switch, to the first terminal of the third capacitor, and to the input of the second inverter; the output of the first inverter is coupled to the second terminals of the fourth switch and the third capacitor, and to a first output terminal of the circuitry; and the output of the second inverter is coupled to the second terminals of the fifth switch and the fourth capacitor, and to a second output terminal of the circuitry.

Claim 24

The circuitry of claim 19 further comprising: sixth and seventh switches each having first and second terminals; the first terminal of the sixth switch is coupled to the second terminal of the first capacitor; the second terminal of the sixth switch is coupled to the first terminal of the fourth switch, to the first terminal of the fourth capacitor, and to the input of the first inverter; the first terminal of the seventh switch is coupled to the second terminal of the second capacitor; and the second terminal of the seventh switch is coupled to the first terminal of the fifth switch, to the first terminal of the third capacitor, and to the input of the second inverter.

Claim 27

The method of claim 21 further comprising the step of: (f) after performing steps (c) and (d), isolating the first and second capacitors from the inputs of the first and second amplifiers, respectively, at a predetermined period of time when a latching of the first and second amplifiers begins.