US5332687A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor memory having a memory cell array and a peripheral circuit portion so as to improve the characteristics of the device
Assignee: Sony Corp
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Filing: 1993-06-09
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Granted: 1994-07-26
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Expires: 2013-06-09
Abstract
Abstract After an insulator film has been formed on an upper layer of a capacitor constituting a memory cell, the insulator film is wet etched using a photo resist covering only a peripheral circuit portion as a mask and using a plate electrode covering the whole of a memory cell array portion as a stopper. For this reason, a step between the memory cell array portion and the peripheral circuit portion, originating from the formation of the capacitor, is moderated by the insulator film retained only in the peripheral circuit portion.
Inventors
- 👤 Hideaki Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:41
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/09; H10B12/30; H10B12/31; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
150 words
A method of manufacturing semiconductor memory device having a memory cell array portion and a peripheral circuit portion wherein each memory cell comprises a transistor and a capacitor, comprising steps of: forming said transistors on a semiconductor substrate of said memory cell array portion; forming said capacitors on said substrate of said memory cell array portion, each capacitor comprising a storage node electrode and a plate electrode provided on said node electrode; forming a first insulator film on the whole of said substrate on which said transistors and said capacitors are provided; forming a photo resist on said first insulator film which corresponds to said peripheral circuit portion; removing said first insulator film provided on said memory cell portion by using said photo resist as a mask; and forming a second insulator film on said plate electrodes of said capacitor and said first insulator film of said peripheral circuit portion.
Claim 2
Independent Claim
150 words
A method of manufacturing semiconductor memory device having a memory cell array portion and a peripheral circuit portion wherein each memory cell comprises a transistor and a capacitor, comprising steps of: forming said transistors on a semiconductor substrate of said memory cell array portion; forming said capacitors on said substrate of said memory cell array portion, each capacitor comprising a storage node electrode and a plate electrode provided on said node electrode; forming a first insulator film on the whole of said substrate on which said transistors and said capacitors are provided; forming a photo resist on said first insulator film which corresponds to said peripheral circuit portion; removing said first insulator film provided on said memory cell portion by using said photo resist as a mask; and forming a second insulator film on said plate electrodes of said capacitor and said first insulator film of said peripheral circuit portion.
Claim 3
Dependent Claim
27 words
A method of manufacturing semiconductor memory device according to claim 1, wherein said first insulator film of said memory cell array portion is removed by wet etching.
Claim 4
Dependent Claim
42 words
A method of manufacturing semiconductor memory device according to claim 1, wherein said first insulator film of said memory cell array portion is removed by using said plate electrodes provided on the whole of said memory cell array portion as a mask.
Claim 5
Dependent Claim
46 words
A method of manufacturing semiconductor memory device according to claim 1, comprising step of; forming a silicon nitride film on said each plate electrode, wherein said first insulator film of said memory cell array portion is removed by using said silicon nitride films as a mask.
Claim 6
Independent Claim
180 words
A method of manufacturing semiconductor memory device having a memory cell array portion and a peripheral circuit portion wherein each memory cell comprises a transistor and a capacitor, comprising steps of: forming said transistors on a semiconductor substrate of said memory cell array portion; forming said capacitors on said substrate of said memory cell array portion, each capacitor comprising a storage node electrode and a plate electrode provided on said node electrode; forming a first insulator film on the whole of said substrate on which said transistors and said capacitors are provided; said first insulator film having a step portion, forming a first photo resist on said step portion of said first insulator film; forming a second photo resist such that an edge of said second photo resist is located on said first photo resist; removing said first insulator film provided on said memory cell portion by using said first and second photo resist as a mask; and forming a second insulator film on said plate electrodes of said capacitor and said first insulator film of said peripheral circuit portion.
Claim 7
Independent Claim
180 words
A method of manufacturing semiconductor memory device having a memory cell array portion and a peripheral circuit portion wherein each memory cell comprises a transistor and a capacitor, comprising steps of: forming said transistors on a semiconductor substrate of said memory cell array portion; forming said capacitors on said substrate of said memory cell array portion, each capacitor comprising a storage node electrode and a plate electrode provided on said node electrode; forming a first insulator film on the whole of said substrate on which said transistors and said capacitors are provided; said first insulator film having a step portion, forming a first photo resist on said step portion of said first insulator film; forming a second photo resist such that an edge of said second photo resist is located on said first photo resist; removing said first insulator film provided on said memory cell portion by using said first and second photo resist as a mask; and forming a second insulator film on said plate electrodes of said capacitor and said first insulator film of said peripheral circuit portion.
Claim 8
Dependent Claim
27 words
A method of manufacturing semiconductor memory device according to claim 5, wherein said first insulator film of said memory cell array portion is removed by wet etching.
Claim 9
Dependent Claim
29 words
A method of manufacturing semiconductor memory device according to claim 5, wherein said first insulator film of said memory cell array portion is removed by an isotropic dry etching.
Claim 10
Dependent Claim
42 words
A method of manufacturing semiconductor memory device according to claim 5, wherein said first insulator film of said memory cell array portion is removed by using said plate electrodes provided on the whole of said memory cell array portion as a mask.
Claim 11
Dependent Claim
46 words
A method of manufacturing semiconductor memory device according to claim 5, comprising step of; forming a silicon nitride film on said each plate electrode, wherein said first insulator film of said memory cell array portion is removed by using said silicon nitride films as a mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
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