Single poly EE cell with separate read/write paths and reduced product term coupling

Claim 1

An electrically erasable and programmable semiconductor memory array in a body of semiconductor material, said array comprising: a plurality of semiconductor memory cells fabricated with a single layer of polycrystalline silicon arranged in rows and columns along a surface of said body, each of said memory cells comprising an electrically programmable and erasable transistor, a read select transistor coupled to said programmable transistor, said read select transistor including a read select gate for controlling the conduction of said read select transistor, a write select transistor coupled to said programmable transistor, said write select transistor including a write select gate for controlling the conduction of said write select transistor; a plurality of first electrically conductive members, each associated with a respective single row of said rows of memory cells and connected to the read select gates of the memory cells in its respective single row; and a plurality of second electrically conductive members, each associated with a respective single row of said rows of memory cells and connected to the write select gates of the memory cells in its respective single row, whereby a first electrical potential is applied to the read select gates of each of said rows of memory cells independently of a second electrical potential applied to the write select gates of each of said rows of memory cells wherein said body of semiconductor material is of a first conductivity type, said read select transistors and write select transistors are defined by regions of a second conductivity type extending into said body from said surface, said array further comprising third electrically conductive members, each having a first level portion for providing electrical connection to said regions of semiconductor material of second conductivity type and a second level portion connected to said first level portion, said second level portion extending substantially parallel to said surface, wherein said first and second electrically conductive members are spaced intermediate said surface of said body and said second level portion of said third electrically conductive members.