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US5331323A
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US
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Analog-to-digital connecter using multi-gate field effect transistors
Assignee: Sharp Corp
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Filing: 1993-05-06
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Granted: 1994-07-19
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Expires: 2013-05-06
Abstract
Abstract The present invention is directed to an analog-to-digital (A/D) converter realized by a small circuit. The A/D converter according to this invention generates a discrete output voltage having several levels in response to an input analog voltage. It includes a number of field effect transistors (FETs), each of which corresponds to an output voltage level and has multiple gates for receiving outputs of higher-order FETs, the input voltage and a negative offset voltage. The A/D converter also includes a voltage divider for generating the offset voltage for each FET and a plurality of inverters corresponding to each FET for outputting a constant positive voltage in response to a negative output of the corresponding FET and for outputting a zero voltage responsive to a positive output voltage of the corresponding FET.
Inventors
- 👤 Makoto Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/42; H02; H02M; H02M1/00; H02M1/08; H03M1/36
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
131 words
An analog-to-digital converter for generating a digital output in response to an analog input voltage, said converter comprising: a plurality of FETs each of which corresponds to a bit of said digital output, each FET having a plurality of gates for receiving outputs of FETs corresponding to more significant bits of said digital output, said analog input voltage and an offset voltage of a first polarity; a voltage divider for generating said offset voltage; and a plurality of inverters, each of which corresponds to an FET, for outputting a constant voltage having a second polarity opposite said first polarity in response to an output of said first polarity of said corresponding FET and for outputting a zero voltage in response to an output of said second polarity of said corresponding FET.
Claim 2
Dependent Claim
131 words
An analog-to-digital converter for generating a digital output in response to an analog input voltage, said converter comprising: a plurality of FETs each of which corresponds to a bit of said digital output, each FET having a plurality of gates for receiving outputs of FETs corresponding to more significant bits of said digital output, said analog input voltage and an offset voltage of a first polarity; a voltage divider for generating said offset voltage; and a plurality of inverters, each of which corresponds to an FET, for outputting a constant voltage having a second polarity opposite said first polarity in response to an output of said first polarity of said corresponding FET and for outputting a zero voltage in response to an output of said second polarity of said corresponding FET.
Claim 3
Dependent Claim
21 words
The converter of claim 1, wherein said first polarity is a negative polarity, and said second polarity is a positive polarity.
Claim 4
Dependent Claim
102 words
An analog-to-digital converter for generating a digital output in response to an analog input voltage, said converter comprising: a voltage divider providing a plurality of offset voltages; a plurality of conversion means, each of said conversion means corresponding to an output bit of said digital output and receiving as inputs said analog input signal, one of said plurality of offset voltages, and first outputs of any of said plurality of conversion means corresponding to higher-order bits of said digital output; wherein each of said plurality of conversion means is for providing an output representative of its corresponding bit of said digital output.
Claim 5
Dependent Claim
102 words
An analog-to-digital converter for generating a digital output in response to an analog input voltage, said converter comprising: a voltage divider providing a plurality of offset voltages; a plurality of conversion means, each of said conversion means corresponding to an output bit of said digital output and receiving as inputs said analog input signal, one of said plurality of offset voltages, and first outputs of any of said plurality of conversion means corresponding to higher-order bits of said digital output; wherein each of said plurality of conversion means is for providing an output representative of its corresponding bit of said digital output.
Claim 6
Dependent Claim
39 words
The converter of claim 3, each of said conversion means comprising: an FET having said analog signal, said one of said plurality of offset voltages, and said first outputs each as an input to a gate of said FET.
Claim 7
Dependent Claim
25 words
The converter of claim 4, wherein each of said FETs has a drain receiving said corresponding offset voltage and a source providing said first output.
Claim 8
Dependent Claim
107 words
The converter of claim 3, said conversion means comprising: comparison means receiving as inputs said analog input signal, said one of said plurality of offset voltages, and said first outputs of any of said plurality of conversion means corresponding to higher-order bits of said digital output, and providing as said first output said one of said plurality of offset voltages when a sum of inputs of said comparison means is positive; and inverter means receiving said first output for providing as said second output a binary-valued signal having a "1" value when said first output is said one of said plurality of offset voltages and "0" otherwise.
Claim 9
Dependent Claim
48 words
The converter of claim 6, each of said comparison means comprising: an FET receiving as inputs said analog input signal, said one of said plurality of offset voltages, and said first outputs of any of said plurality of conversion means corresponding to higher-order bits of said digital output.
Claim 10
Dependent Claim
13 words
The converter of claim 3, said voltage divider comprising a binary-weighted resistor ladder.
Claim 11
Dependent Claim
28 words
The converter of claim 3, wherein said analog input signal and said second outputs are opposite in polarity to said plurality of offset voltages and said first outputs.
Claim 12
Dependent Claim
28 words
The converter of claim 9, wherein said analog input signal and said second outputs are positive and said plurality of offset voltages and said first outputs are negative.
References Cited (Backward Citations)
US4547763A
Cited
US5117235A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |