Manufacturing process for a micro MIS type FET

Claim 1

A process of manufacturing a micro MIS type FET comprising the steps of: preparing a semiconductor layer having a first conductivity type at least in a region from a surface to a predetermined depth of a semiconductor substrate, selectively forming an isolation insulating film on said semiconductor substrate to form a semiconductor composite, subjecting said semiconductor composite to epitaxial growth conditions whereby an epitaxial layer is formed at least above said semiconductor layer, growing a first conductivity type threshold voltage control region in the surface of said substrate, said region having an impurity concentration of more than 1×10 17 /cm 3 , growing a first conductivity type epitaxial layer having a thickness of less than 100 nm and an impurity concentration of less than 1×10 16 /cm 3 on said surface of said semiconductor layer to over said isolation insulation film, and forming second conductivity type source/drain regions mutually spaced apart by a distance of less than 2 μm having a depth exceeding the distance from the top surface of said epitaxial layer to the bottom of said epitaxial layer, said source/drain regions extending into portions of said epitaxial layer over said isolation insulating film, whereby a channel layer with a length of less than 2 μm having an impurity concentration of less than 1×10 16 /cm 3 is formed above said threshold voltage control region between said source/drain regions in said substrate surface, a lower boundary of said channel layer having a depth less than depths of said source/drain regions, said substrate having an abrupt change in impurity concentration at said lower boundary of said channel layer.