US5329631A — Microprocessor system for effectively using a par…

Claim 1

Independent Claim 266 words

A microprocessing system for extending an address space, comprising: a basic semiconductor memory having a first address space formed by a one chip memory and a second address space formed by at least one memory chip, said first address space including a part for storing at least one of a program and data before startup of the microprocessing system; an extended semiconductor memory re-using said part of the first address space as an extended address space after startup of the microprocessing system to address said extended semiconductor memory; system start up indicating means for indicating whether said microprocessing system is in a system start up state; a microprocessor, connected to said basic and extended semiconductor memories to directly address the first and second address spaces and operatively connected to said system start up indicating means, said microprocessor comprising reading and writing means for reading said one of the program and the data from said part of said first address space and for writing said one of the program and the data into said second address space when said system start up indicating means indicates that said microprocessing system is in the system start up state; and address extending hard register means, connected to said microprocessor, having the address located in said second address space, for storing an extended address for accessing said extended semiconductor memory instead of accessing said part of said first address space when said system start up indicating means indicates that said microprocessing system is not in the system start up state and when said part of said first address space is addressed.

Claim 2

Dependent Claim 266 words

A microprocessing system for extending an address space, comprising: a basic semiconductor memory having a first address space formed by a one chip memory and a second address space formed by at least one memory chip, said first address space including a part for storing at least one of a program and data before startup of the microprocessing system; an extended semiconductor memory re-using said part of the first address space as an extended address space after startup of the microprocessing system to address said extended semiconductor memory; system start up indicating means for indicating whether said microprocessing system is in a system start up state; a microprocessor, connected to said basic and extended semiconductor memories to directly address the first and second address spaces and operatively connected to said system start up indicating means, said microprocessor comprising reading and writing means for reading said one of the program and the data from said part of said first address space and for writing said one of the program and the data into said second address space when said system start up indicating means indicates that said microprocessing system is in the system start up state; and address extending hard register means, connected to said microprocessor, having the address located in said second address space, for storing an extended address for accessing said extended semiconductor memory instead of accessing said part of said first address space when said system start up indicating means indicates that said microprocessing system is not in the system start up state and when said part of said first address space is addressed.

Claim 3

Dependent Claim 168 words

A microprocessing system as claimed in claim 1, further comprising: first gate means for generating a first enable signal for enabling said first address space of said basic semiconductor memory when said system start up indicating means indicates that said part of said first address space of said basic semiconductor memory is to be used and when an address signal generated and received from said microprocessor designates said part of said first address space; and second gate means for enabling said extended semiconductor memory when said system start up indicating means indicates that said extended address space is to be used and when said address signal generated by and received from said microprocessor designates said part of said first address space, wherein, when said address signal generated from said microprocessor designates said first address space other than said part of said first address space, said first address space is selected even when said system start up indicating means indicates that said extended address space is to be used.

Claim 4

Dependent Claim 77 words

A microprocessing system as claimed in claim 1, wherein said address extending hard register means comprises an address extending memory in said second address space, and the extended address is stored in said address extending memory of said address extending hard register means when said microprocessor generates an address signal for designating an address of said address extending memory in the second address space and said extended address is written from said microprocessor as extended address data.

Claim 5

Dependent Claim 50 words

A microprocessing system as claimed in claim 3, further comprising a decoder for decoding an address signal generated by said microprocessor to access said address extending hard register means when said microprocessor accesses the one of the data and the program in one of said basic and extended semiconductor memories.

Claim 6

Dependent Claim 44 words

A microprocessing system as claimed in claim 4, wherein said extended address space comprises a plurality of blocks, and said extended address stored in said address extending memory designates one of said plurality of blocks in response to said data generated by said microprocessor.

Claim 7

Dependent Claim 20 words

A microprocessing system as claimed in claim 5 wherein said first address space is formed by a read only memory.

Claim 8

Dependent Claim 158 words

A microprocessing system as claimed in claim 6, further comprising: first gate means for generating a first enable signal for enabling said read only memory when said system start up indicating means indicates that said part of said first address space is to be used and when said address signal generated and received from said microprocessor designates said part of said first address space; and second gate means for enabling said extended semiconductor memory when said system start up indicating means indicates that said extended address space is to be used and when said address signal received from said microprocessor designates said part of said first address space, wherein said read only memory is selected, even when said system start up indicating means indicates that said extended address space is to be used when said address signal received from said microprocessor designates another part of said first address space other than said part of said first address space.

Claim 9

Dependent Claim 24 words

A microprocessing system as claimed in claim 7 wherein said address extending hard register means has a second address in said first address space.

Claim 10

Dependent Claim 80 words

A microprocessing system as claimed in claim 8 wherein said address extending hard register means is selected to generate a register flag in said system start up indicating means and said extended address, when said microprocessor generates the address signal for designating a memory address in said read only memory or the address in said second address space, and when said first address of said system-start up indicating means in said first address space is designated by said address signal.

Claim 11

Dependent Claim 33 words

A microprocessing system as claimed in claim 9, wherein said address extending hard register means is said address extending memory for providing said extended address set by the data generated by said microprocessor.

Claim 12

Dependent Claim 35 words

A microprocessing system as claimed in claim 10, wherein said address extending memory is enabled when said microprocessor generates the address signal for designating said address extending hard register means in said second address space.

Claim 13

Dependent Claim 20 words

A microprocessing system as claimed in claim 1 wherein said second address space is formed by a random access memory.

Claim 14

Dependent Claim 19 words

A microprocessing system as claimed in claim 1 wherein said extended memory is formed by a read only memory.

Claim 15

Dependent Claim 240 words

A microprocessor system for effectively using a part of an address space, comprising: a basic semiconductor memory having a first area and a second area for storing at least one of a program and data before an initial program load of the microprocessor system; an extended semiconductor memory having a plurality of memory blocks each having the same capacity; a designating register connected to said extended semiconductor memory and having contents for designating each of said plurality of memory blocks; and a central processing unit, connected to said basic and extended semiconductor memories and operatively connected to said designating register, the first and second areas of said basic semiconductor memory and the memory blocks of said extended semiconductor memory being directly addressable by said central processing unit which designates said designating register after the initial program load and designates one of said plurality of memory blocks in said extended semiconductor memory based on the contents of said designating register, so that a first area in said basic semiconductor memory and each of the memory blocks in said extended memory are enabled to be accessed, said central processing unit including reading and writing means for reading, during the initial program load, said at least one of the program or the data from the second area in said basic semiconductor memory and writing said at least one of the program or the data to the first area in said basic semiconductor memory.

Claim 16

Dependent Claim 240 words

A microprocessor system for effectively using a part of an address space, comprising: a basic semiconductor memory having a first area and a second area for storing at least one of a program and data before an initial program load of the microprocessor system; an extended semiconductor memory having a plurality of memory blocks each having the same capacity; a designating register connected to said extended semiconductor memory and having contents for designating each of said plurality of memory blocks; and a central processing unit, connected to said basic and extended semiconductor memories and operatively connected to said designating register, the first and second areas of said basic semiconductor memory and the memory blocks of said extended semiconductor memory being directly addressable by said central processing unit which designates said designating register after the initial program load and designates one of said plurality of memory blocks in said extended semiconductor memory based on the contents of said designating register, so that a first area in said basic semiconductor memory and each of the memory blocks in said extended memory are enabled to be accessed, said central processing unit including reading and writing means for reading, during the initial program load, said at least one of the program or the data from the second area in said basic semiconductor memory and writing said at least one of the program or the data to the first area in said basic semiconductor memory.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-07-11	1998-01-10	1998-07-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-07-11	2002-01-10	2002-07-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-07-11	2006-01-10	2006-07-12	$7700.00	Window Closed / Lapsed

Microprocessor system for effectively using a part of an address space

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