Microprocessor which optimizes bus utilization based upon bus speed

Claim 1

A digital computing system comprising: instruction execution and sequencing means for executing each of a plurality of instructions and for determining a sequence of instruction execution, the instruction execution and sequencing means further comprising: i) instruction pipe means for storing a plurality of instructions; ii) pipe controller means coupled to the instruction pipe means for monitoring the instruction pipe means and for providing prefetch request signals; and iii) operand request means for providing operand read/write request signals; bus controller means coupled to the instruction execution and sequencing means for receiving the prefetch request signals and the operand read/write request signals and for operating a communication bus to perform prefetch bus cycles and operand read/write bus cycles, the bus controller means further comprising: i) bus cycle scheduler means for determining whether to commence a prefetch bus cycle, commence an operand read/write bus cycle or to commence no bus cycle; wherein the improvement comprises: the bus controller further comprises bus speed determination means for determining a time required to complete a previously completed bus cycle and for providing a bus speed signal; and the pipe controller means is coupled to the bus speed determination means to receive the bus speed signal and is for determining whether to provide the prefetch request signal based on a value of the bus,speed signal.