Dynamic semiconductor memory with refresh function

Claim 2

A dynamic semiconductor memory comprising: a refresh mode identifying circuit for producing a refresh mode signal of active level when said identifying circuit detects that a mode is a refresh mode; a refresh address signal generating circuit for generating a refresh address signal if said refresh mode signal is of active level; a switch circuit for selecting said refresh address signal if said refresh mode signal is of active level while selecting an external address signal if said refresh mode signal is of inactive level; a plurality of memory cell arrays each having a plurality of memory cells, word lines and bit lines; an internal control signal producing circuit for producing a plurality of activation control signals each of which is associated with each of said memory cell arrays and becomes to be of activated level at a predetermined timing; a plurality of row selecting circuits for being activated when said associated activation control signal is of activated level, to put a predetermined word line in said associated memory cell array to be on selection level in accordance with an address signal generated from said switch circuit; and a plurality of sense amplifying circuits for being activated when said associated activation control signal is of activated level, to amplify and rewrite data stored in a memory cell which connects with a word line of selection level of associated memory cell array.

Claim 3

The dynamic semiconductor memory in accordance with claim 1, wherein said internal control signal producing circuit is provided with activation level controlling means for externally programming timing at which said activation control signals become to be of activated level.

Claim 4

The dynamic semiconductor memory in accordance with claim 2, wherein said activation level controlling means is a programing circuit using a fuse or transistor.

Claim 5

The dynamic semiconductor memory in accordance with claim 1, wherein said memory cell arrays are of two, said activation control signals are of two, said row selecting circuits are of two each having a row decoder and a word driving circuit, and said sense amplifying circuits are of two.

Claim 6

The dynamic semiconductor memory in accordance with claim 1, wherein said memory cell arrays and said activation control signals are of four, respectively, said row selecting circuits have two row decoders and four word driving circuits, each of said two row decoders being connected to the two word driving circuits, and said sense amplifying circuits are of four.

Claim 7

A dynamic semiconductor memory comprising: a buffer circuit for receiving row address control signals and column address control signals and buffer amplifying said row and column address control signals; a refresh mode identifying circuit for producing a refresh mode signal of active level when said identifying circuit detects that a mode is a refresh mode on the basis of output signals transferred from said buffer circuit; a refresh address signal generating circuit for generating a refresh address signal if said refresh mode signal is of active level; an address buffer circuit for receiving an external address signal to output external row and column address signals; a switch circuit for selecting said refresh address signal if said refresh mode signal is of active level while selecting said external row address signal if said refresh mode signal is of inactive level; two memory cell arrays each having a plurality of memory cells, word lines and bit lines; an internal control signal producing circuit for receiving said output signals transferred from said buffer circuit, said refresh mode signal and timing signal transferred from said refresh address signal generating circuit to produce two activation control signals each of which is associated with each of said memory cell arrays and becomes to be of activated level at a predetermined timing; two row selecting circuits for being activated when said associated activation control signal is of activated level, to put a predetermined word line in said associated memory cell array to be on selection level in accordance with an address signal generated from said switch circuit; two sense amplifying circuits for being activated when said associated activation control signal is of activated level, to amplify and rewrite data stored in a memory cell which connects with a word line of selection level of associated memory cell array; a column decoder for selecting a predetermined bit line in said associated memory cell array in accordance with said external column address signal; and an input and output circuit for transferring data, which is externally input and to be written therein, to the selected bit line and outputting readout data transferred through said selected bit line.

Claim 8

A dynamic semiconductor memory comprising: a buffer circuit for receiving row address control signals and column address control signals and buffer amplifying said row and column address control signals; a refresh mode identifying circuit for producing a refresh mode signal of active level when said identifying circuit detects that a mode is a refresh mode on the basis of output signals transferred from said buffer circuit; a refresh address signal generating circuit for generating a refresh address signal if said refresh mode signal is of active level; an address buffer circuit for receiving an external address signal to output external row and column address signals; a switch circuit for selecting said refresh address signal if said refresh mode signal is of active level while selecting said external row address signal if said refresh mode signal is of inactive level; two memory cell arrays each having a plurality of memory cells, word lines and bit lines; an internal control signal producing circuit for receiving said output signals transferred from said buffer circuit, said refresh mode signal and timing signal transferred from said refresh address signal generating circuit to produce two activation control signals each of which is associated with each of said memory cell arrays and becomes to be of activated level at a predetermined timing; two row selecting circuits for being activated when said associated activation control signal is of activated level, to put a predetermined word line in said associated memory cell array to be on selection level in accordance with an address signal generated from said switch circuit; two sense amplifying circuits for being activated when said associated activation control signal is of activated level, to amplify and rewrite data stored in a memory cell which connects with a word line of selection level of associated memory cell array; a column decoder for selecting a predetermined bit line in said associated memory cell array in accordance with said external column address signal; and an input and output circuit for transferring data, which is externally input and to be written therein, to the selected bit line and outputting readout data transferred through said selected bit line.

Claim 9

The dynamic semiconductor memory in accordance with claim 6, wherein said internal control signal producing circuit is provided with activation level controlling means for externally programming timing at which said activation control signals become to be of activated level.

Claim 10

The dynamic semiconductor memory in accordance with claim 6, wherein each of said row selecting circuits comprises a row decoder and a word driving circuit.

Claim 11

A dynamic semiconductor memory comprising: a buffer circuit for receiving row address control signals and column address control signals and buffer amplifying said row and column address control signals; a refresh mode identifying circuit for producing a refresh mode signal of active level when said identifying circuit detects that a mode is a refresh mode on the basis of output signals transferred from said buffer circuit; a refresh address signal generating circuit for generating a refresh address signal if said refresh mode signal is of active level; an address buffer circuit for receiving an external address signal to output external row and column address signals; a switch circuit for selecting said refresh address signal if said refresh mode signal is of active level while selecting said external row address signal if said refresh mode signal is of inactive level; four memory cell arrays each having a plurality of memory cells, word lines and bit lines; an internal clock producing circuit for receiving said output signals transferred from said buffer circuit, said refresh mode signal and timing signal transferred from said refresh address signal generating circuit to produce four activation control signals each of which is associated with each of said memory cell arrays and becomes to be of activated level at a predetermined timing; four row selecting circuits for being activated when said associated activation control signal is of activated level, to put a predetermined word line in said associated memory cell array to be on selection level in accordance with an address signal generated from said switch circuit; four sense amplifying circuits for being activated when said associated activation control signal is of activated level, to amplify and rewrite data stored in a memory cell which connects with a word line of selection level of associated memory cell array; two column decoders for selecting a predetermined bit line in said associated memory cell array in accordance with said external column address signal; and an input and output circuit for transferring data, which is externally input and to be written therein, to the selected bit line and outputting readout data transferred through said selected bit line.

Claim 12

A dynamic semiconductor memory comprising: a buffer circuit for receiving row address control signals and column address control signals and buffer amplifying said row and column address control signals; a refresh mode identifying circuit for producing a refresh mode signal of active level when said identifying circuit detects that a mode is a refresh mode on the basis of output signals transferred from said buffer circuit; a refresh address signal generating circuit for generating a refresh address signal if said refresh mode signal is of active level; an address buffer circuit for receiving an external address signal to output external row and column address signals; a switch circuit for selecting said refresh address signal if said refresh mode signal is of active level while selecting said external row address signal if said refresh mode signal is of inactive level; four memory cell arrays each having a plurality of memory cells, word lines and bit lines; an internal clock producing circuit for receiving said output signals transferred from said buffer circuit, said refresh mode signal and timing signal transferred from said refresh address signal generating circuit to produce four activation control signals each of which is associated with each of said memory cell arrays and becomes to be of activated level at a predetermined timing; four row selecting circuits for being activated when said associated activation control signal is of activated level, to put a predetermined word line in said associated memory cell array to be on selection level in accordance with an address signal generated from said switch circuit; four sense amplifying circuits for being activated when said associated activation control signal is of activated level, to amplify and rewrite data stored in a memory cell which connects with a word line of selection level of associated memory cell array; two column decoders for selecting a predetermined bit line in said associated memory cell array in accordance with said external column address signal; and an input and output circuit for transferring data, which is externally input and to be written therein, to the selected bit line and outputting readout data transferred through said selected bit line.

Claim 13

The dynamic semiconductor memory in accordance with claim 9, wherein said internal clock producing circuit is provided with activation level controlling means for externally programming timing at which said activation control signals become to be of activated level.