Patent US5329281A successfully refreshed from Google Patents.
US5329281A
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Analog to digital converter with autoranging offset
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1993-04-26
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Granted: 1994-07-12
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Expires: 2013-04-26
Abstract
Abstract A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.
Inventors
- 👤 Richard A. Baumgartner
- 👤 Charles E. Moore
- 👤 Earl C. Herleikson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:10
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/004; H03M1/005; A; A61; A61B; A61B5/00; A61B5/24; A61B5/30; A61B5/305; A61B5/72; A61B5/7203; G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/1865; H03F; H03F3/00; H03F3/005; H03F3/38; H03F3/387; H03F3/393; H03M1/12; H03M1/18; H03M1/181; H03M3/00; H03M3/30; H03M3/39; H03M3/392; H03M3/398; H03M3/458; H03M3/478; H03M3/488; A61B5/7235; A61B5/7242; H03F2200/00; H03F2200/261; H03F2200/331; H03M1/50; H03M1/504; H03M3/48
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
98 words
An analog to digital conversion circuit comprising: summation means for generating a sum of an analog signal input and an analog offset input; analog to digital converter means, connected to the summation means, for converting the sum to a digital signal output; and offset means, connected to the digital signal output and receiving a predetermined threshold and a predetermined number, for generating the analog offset input, wherein the offset means generates the analog offset input if the digital signal output exceeds the predetermined threshold for the predetermined number of consecutive conversions of the analog to digital converter means.
Claim 2
Dependent Claim
98 words
An analog to digital conversion circuit comprising: summation means for generating a sum of an analog signal input and an analog offset input; analog to digital converter means, connected to the summation means, for converting the sum to a digital signal output; and offset means, connected to the digital signal output and receiving a predetermined threshold and a predetermined number, for generating the analog offset input, wherein the offset means generates the analog offset input if the digital signal output exceeds the predetermined threshold for the predetermined number of consecutive conversions of the analog to digital converter means.
Claim 3
Dependent Claim
54 words
An analog to digital conversion circuit as in claim 1 wherein the predetermined threshold further comprises: an upper threshold, wherein the offset means generates a negative analog offset input of the digital signal output is greater than the upper threshold for the predetermined number of consecutive conversions of the analog to digital converter means.
Claim 4
Dependent Claim
54 words
An analog to digital conversion circuit as in claim 2 wherein the predetermined threshold further comprises: a lower threshold, wherein the offset means generates a positive analog offset input if the digital signal output is less than the lower threshold for the predetermined number of consecutive conversions of the analog to digital converter means.
Claim 5
Dependent Claim
103 words
An analog to digital conversion circuit as in claim 3 wherein the offset means further comprises: an offset counter having a digital offset output; and digital to analog converter means for converting the digital offset output to the analog offset input, wherein the offset counter is incremented if the digital signal output is greater than the upper threshold for the predetermined number of consecutive conversions of the analog to digital converter means and the offset digital counter is decremented if the digital output is less than the lower threshold for the predetermined number of consecutive conversions of the analog to digital converter means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |